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A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.

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0
16 bits .!

Instruction Opcode Size $= \log_2 40 = 6$

Register operand size $= \log_224 =5$

Total bits available $= 32$

Bits required for opcode $+$ two register operands $= 6 + 2 \times 5 = 16$

Bits available for immediate operand $= 32 - 16 = 16.$
by Boss (41.9k points)
edited
+15

|--------------------------------------- 32-bits -----------------------------------------------------------------|

 opcode(6) R1(5) R2(5) immediate operand =?

6+5+5+x=32 bits

x=16 bits

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Fantastic answer. That solves GATE 2016 set 2 questions .thankyou.
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Opcode  tell no of distinct operation are their e.g add,sub etc .so why we using log40 as opcode 40 are the distinct instruction.
+1

rajinder singh

There are 40 opcodes, it means, there will be 40 distinct operations like ADD, SUB, MUL etc...So in order to represent one operation, we need some bits right!!! If we have 4 distinct operations like ADD, MUL, DIV, SUB, we have to represent each operation with some bits, here we need two bits.

01-MUL

10-DIV

11-SUB

So we need log24  = 2 bits

Similarly, in this question, we have 40 distinct opcodes, so in order to name them in binary

we need log240 = 6 bits

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But ln question they given  40 distinct instruction not 40 distinct operation then how you taken as 40 operation .If you think that it should be 40 operation then their might be chance that in 40distinct instructions  2 , 3 instruction can have same operation.
16 bits
by Active (2.5k points)
log 40=6

log 24=5

6+5*2=16

by (11 points)

For 40 distinct instructions :

no. of bits need = Ceil (log(40)) =6

no. of bits need for 1 register =Ceil (log(24)) = 5

for another register = 5

for immediate operand :

no. of bits = 32-(6+5+5) = 16

 6 5 5 16

op code       R1               R2          immediate

by Junior (987 points)