GATE CSE 2016 Set 2 | Question: 33

Question

Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.

Comments

As simple as possible

 

$T_{1}$ is 2 times $T_{3}$ $\Rightarrow$ $T_{1}$ > $T_{3}$

$T_{1}$ is $\frac{3}{4}$th of $T_{2}$ $\Rightarrow$ $T_{2}$ > $T_{1}$

these two implies $T_{2}$ > $T_{1}$ > $T_{3}$

So time taken by 2nd stage ( ie $T_{2}$ ) is used to calculate frequency of the processor. $\Rightarrow$ $T_{2}$ = $\frac{1}{3}$

Let $T_{1}$ = K , which implies

$T_{3}$ = $\frac{K}{2}$

$T_{2}$ = $\frac{4}{3}$K  = $\frac{1}{3}$ $\Rightarrow$ K = $\frac{1}{4}$

 

We will now split $T_{2}$ ( ie $\frac{4}{3}$K  ) into 2 stages as $T_{21}$ =  $\frac{2}{3}$K  and $T_{22}$ = $\frac{2}{3}$K

 

Now we have four stages

$T_{1}$ = K

$T_{21}$ = $\frac{2}{3}$K

$T_{22}$ = $\frac{2}{3}$K

$T_{3}$ = $\frac{K}{2}$

Out of these four stages $T_{1}$ is largest. $T_{1}$ = K = $\frac{1}{4}$. So the new frequency is 4. (GHz)

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$4T_{1}$ = $3T_{2}$ = $8T_{3}$

$T_{1}:T_{2}:T_{3}$ = $\frac{1}{4} :\frac{1}{3}:\frac{1}{8}$

$\frac{x}{3}$ = $\frac{1}{3G}$

x = $\frac{1}{G}$

T2 is the highest & divided into two stages, So it becomes $\frac{1}{6}$

Now, Highest is $\frac{1}{4}$

So $\frac{1}{\frac{x}{4}}$ = 4G

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brilliant solution

Answer 1

ANS.4

Comments

I got 4.08...will this be considered?

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no

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Yes that would be considered

In the key, range was from 3.9 to 4.1

Answer 2

 

We can also find the t1, t2 and t3 and then find the new stages and their cycle time and then finally new frequency.

Answer 3

Hence, answer is 4GHz

Answer 4

it has 3 pipeline stage and processor has 3 GHz.

now the time period of clock =1/3 ns.

now say stage latency T3 =x

so T1=2x

T2= 8x/3.

now the delay is non uniform so we choose the maximum for the processor clock to synchronize.

so 8x/3=1/3

x=1/8.

now T1=¼ ns

T2 =1/3 ns

T3=1/8 ns

now according to question T2 is maximum so it spilt in two equal part .

T1=¼ ns

T2=1/6 ns

T3=1/6 ns

T4=1/8 ns

now in these new pipeline system T1 has maximum time period so it is chosen to be new processor clock.

clock frequency =1/ time period =1/0.25 =4 GHz