edited by
18,982 views
75 votes
75 votes
Consider a $3 \ \text{GHz}$ (gigahertz) processor with a three stage pipeline and stage latencies $\large\tau_1,\tau_2$ and $\large\tau_3$ such that $\large\tau_1 =\dfrac{3 \tau_2}{4}=2\tau_3$. If the longest pipeline stage is split into two pipeline stages of equal latency , the new frequency is __________ $\text{GHz}$, ignoring delays in the pipeline registers.
edited by

8 Answers

Best answer
151 votes
151 votes

Answer is 4 GHz.

Given $3$ stage pipeline , with $3\text{ GHz}$ processor.

Given , $e_1 =\dfrac{3e_2}{4}=2e_3$

Put $e_1 = 6x$ 

  we get, $e_2 = 8x\  , e_3 = 3x$

Now largest stage time is $8x$.

So, frequency is $\dfrac{1}{8x}$

$\Rightarrow\dfrac{1}{8x}=3 \text{GHz}$  

$\Rightarrow\dfrac{1}{x}=24\text{ GHz}\quad \rightarrow (1)$


Now, we divide $e_2$  into two stages  of $4x\ \&\ 4x.$

New processor has $4$ stages -

$6x,\ 4x,\ 4x,\ 3x.$

Now largest stage time is $6x$.

So, new frequency is 

$\dfrac{1}{6x}$ = $\dfrac{24}{6}$ =  4 GHz (Ans)  $[\because \text{from}\; (1)]$ 

edited by
5 votes
5 votes
Consider, for first case t1=k, t2=4k/3, t3=k/2

Now, for n instructions time to complete the execution is with $3 * 10^9$ Hz clock speed is $n * (1/3) * 10 ^{-9} (\because CPI = 1 $ for pipelined processors).

According to 3-stage pipeline time for n instructions would be :${k}+{4k/3}+{k/2}+{{(n-1)} *{4k/3}}$

by equating these two

$n * (1/3) * 10 ^{-9} {=} {k}+{4k/3}+{k/2}+{{(n-1)} *{4k/3}} $

$ \therefore  (1/3) * 10 ^{-9} {=} {k/n}+{k/2n}+{4k/3} $

So if n is very large we can do,

 $ \lim _ {n \to \infty  } \left ( (1/3) * 10 ^{-9} {=} {k/n}+{k/2n}+{4k/3} \right ) $

By solving this,

$ (1/4) * 10 ^{-9} {=} {k}$

 

Now, we divide 2nd stage so t1=k, t2=2k/3,t3=2k/3, t4=k/2

Consider x to be the resultant frequency or clock speed.

By following the exact same procedure as above, Taking longest pipeline stage as stage 1.

${1/x} {=} {k}$

$ \therefore x {=} {1/k}$

$\therefore x {=} {4 * 10^{9}}$

which is 4 GHz.
edited by
4 votes
4 votes

here frequency=3GHZ 

cycle time =1/frequency=1/3 *10^-9 sec

here pipeline has 3 stages and stage delay is given as : 

τ1  = 3/4τ= 2τ

now equate all stage delay in terms of τ1, so that we can distinguish the largest delay .

and that is :τ1  = 4/3 τ= 1/2 τ1

so here we got  4/3 τ1 is the largest delay.(  number of input is not given so we are assuming it would be a very lage number .)

time taken by pipeline is : (K+n-1)cycle time ,  where( cycle time = largest stage delay+buffer delay + some extra overhead ) and we have only stage delay so cycle time will be that only .now we can write it as :

n*4/3 τ1  =  n* 3*10^-9  ( n is very large so rest calculation with it will be negligible )

and here we got , τ1 =1/4 * 10^-9 ,

split the  largst stage in two stages with equal delay :

stage1= τ1 ,stage 2= 4/6 τ1 stage 3 = 4/6 τ1 , stage4  τ1/2  

and  the largest delay = cycle time is now τ1  which is 1/4 *10^9

so frequency = 4GHZ

Answer:

Related questions

50 votes
50 votes
4 answers
2
Akash Kanase asked Feb 12, 2016
17,640 views
The width of the physical address on a machine is $40$ bits. The width of the tag field in a $512$ KB $8$-way set associative cache is ________ bits.