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113 votes
113 votes

We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

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Best answer
137 votes
137 votes

We need four JK flipflops.
$0\to 1\to0\to2\to0\to3$
$0000\to0001\to0100\to0010\to1000\to0011$

There are $6$ states and $3$ of them correspond to same states.

  • To differentiate between $0,1,2,3$ we need $2$ bits.
  • To differentiate between $3$ $0's$ we need another $2$ bits.

So, total $4\text{-bits}\to 4\;\text{FFs}$

Edit:
whether using extra combinational logic for output is allowed in a counter?
Page No. $10/11$ http://textofvideo.nptel.iitm.ac.in/117105080/lec23.pdf or archive

Now, if you see the counters, now a counter we can define in this way the counter is a degenerate finite state machine, where the state is the only output. So, there is no other primary output from this machine, so the counter is defined like that.

ALSO

Page No. $3$ http://textofvideo.nptel.iitm.ac.in/117106086/lec24.pdf or archive

Counter you know what counter it is, that’s what we want we count the output of counter what is the particular count what is the current count that is the output of a count so no external output. The counter is a case of a state machine in which there are no external inputs, no external outputs. 

Page No. $10$ http://textofvideo.nptel.iitm.ac.in/117106086/lec24.pdf or archive



At $35:30$ www[dot]youtube[dot]com/watch?v=MiuMYEn3dpg

Here In Counter, we cannot use external variable, that purpose will be served by FF's only
We have four distinct states $0,1,2,3$ so, $2 FF$ for them for $3\;0's$ to distinguish we need $2$ more $\text{FFs}$ http://www.youtube.com/watch?v=MiuMYEn3dpg

$4\;\text{FF}$ required.

edited by
22 votes
22 votes

I am using two AND gates and a NOT gate along with 3 flip flops.

there are 6 unique states. lets assume there is a  synchronous counter the generates below sequence:

100->001->101->010->110->011->100.

Let output of 3 flip flops be S1, S2 , S3. Take them through below circuit  

S1 S2  S3  A  B  
1 0 0 1 0 0
0 0 1 0 0 1
1 0 1 1 0 0
0 1 0 0 1 0
1 1 0 1 0 0
0 1 1 0 1 1

if we take B C as final output we can generate 0->1->0->2->0->3. 

So I think it is possible with 3 flip flops.

Requesting comments.

edited by
14 votes
14 votes
IISC Answered it as either 3 or 4 . Both are correct . As seen , 2 bits are required to differentiate 3 Zeros hence 4 bits = 4FF

Also , someone may think it as 6 states and hence 2^3 = 8 >=6 Hence 3 is also correct .

Please note that these questions are repeatedly getting asked . We have to understand that only distinct states can be designed since we dont have dont care input in excitaion table. and hence we should not get confused. First make the states dinsinct with minimum bits. Similar question was asked in GATE 2015 . Please check .
3 votes
3 votes
2 flip flops are required
Answer:

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