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The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.
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Data count register gives the number of words the DMA can transfer in a single cycle..

Here it is $16$ bits.. so max $2^{16}$ words can be transferred in one cycle..

Since memory is byte addressable.. $1 \text{ word}=1\;\text{byte}$
                                                so $2^{16}$ bytes in $1$ cycle..
Now for the given file..
                               File size $=29154\ \textsf{KB} = 29154\times 2^{10}\ \textsf{B}$
                                                  $1$ cylce $\rightarrow$ DMA transfers $2^{16}\ \textsf{B}$
i.e 
                                             $1\ B$ transfered by DMA $\rightarrow \dfrac{1}{2^{16}}$ cycles.

Now, for full file of size $29154\ \textsf{KB},$

Minimum number of cylces $=\dfrac{(29154\times 2^{10}\ B)}{2^{16}}= 455.53$

But number of cylces is asked so $455.53\rightarrow 456.$

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Size of data count register of the DMA controller = 16 bits

Data that can be transferred in one go = 216 bytes = 64 kilobytes File size to be transferred = 29154 kilobytes.

So, number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory = ceil(29154/64) = 456  

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