A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual-to-physical address translation, where the virtual address is used as follows
bits 30-31 are used to index into the first level page table,
bits 21-29 are used to index into second level page table
bits 12-20 are used to index into third level page table
bits 0-11 are used as offset within the page
The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page table are respectively
(A) 20,20 and 20 (B)24,24 and 24 (C) 24,24 and 20 (D) 25,25 and 24
