4 two input NAND gates
F = (x' + y').z + (x' +y').w
= (xy)'.z + (xy)'.w
= ( ( (xy)'.z )' . ( (xy)'.w )' )'
We can tie the inputs 'x' and 'y' to 1st NAND gate to implement the function (xy)' and the output of this gate can be connected to the inputs of the 2nd and 3rd NAND gate.The other remaining input of the 2nd and 3rd NAND gate will be 'w' and 'z'.The output of 2nd and 3rd NAND gate will than be connected to the inputs of the 4th NAND gate.