The size to transfer a block is always decided by source(Do not confuse yourself by looking "a block is transferred from L2 cache to L1 cache). In this case first 16 words will be transferred from main memory to L2 cache( IF nothing is mentioned, the last level cache L2 & main memory page size considered to be equal.) then only 4 words will be transferred from L2 to L1 not the whole block of L2. Now the only confusion is "This whole process of transferring block is a concurrent process or serial?".
If nothing is mentioned in the question then take serial transfer of block (in computer science we always strive for Worst case) so
1) 200ns to access main memory and 20ns to store in the L2 cache.
2) Point (1) will happen for 4 times because of data bus = 4 words, so 16 words will be transferred in 4 times.
3) and after that 20ns to access or read L2 cache and 2ns to place or write it into L1 cache.
so answer would be
4*(200+20) + 20 + 2 = 902.