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A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ nanoseconds, $20$ nanoseconds and $200$ nanoseconds for $L1$ cache, $L2$ cache and the main memory unit respectively.

 

When there is a miss in both $L1$ cache and $L2$ cache, first a block is transferred from main memory to $L2$ cache, and then a block is transferred from $L2$ cache to $L1$ cache. What is the total time taken for these transfers?

  1. $222$ nanoseconds
  2. $888$ nanoseconds
  3. $902$ nanoseconds
  4. $968$ nanoseconds
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8 Answers

Best answer
133 votes
133 votes
The transfer time should be $4*200 + 20 = 820$ ns. But this is not in option. So, I assume the following is what is meant by the question.

$L2$ block size being $16$ words and data width between memory and $L2$ being $4$ words, we require $4$ memory accesses(for read) and $4$ $L2$ accesses (for store). Now, we need to send the requested block to $L1$ which would require one more $L2$ access (for read) and one $L1$ access (for store). So, total time

$= 4 * (200 + 20) +  (20 + 2)$

$= 880 + 22$

$= 902 \ ns$

Correct Answer: $C$
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25 votes
25 votes

scene 1

  • L2 block size is 16 words
  • Data width between l2 and Main Memory is 4 words
    $\Rightarrow$ We need 4 access to Read from Memory and 4 access to store to L2
     To Read from MM require 200ns and To Store in L2 require 20 ns
     Total Time spent : 220 ns

scene 2

  • stored information from L2 is read and stored on L1
  •  Read from L2 takes 20ns and store on L1 takes 2 ns
     $\Rightarrow$  Total time spent in scene - 2 is  22ns

scene 1 and scene 2 can occur simultaneously which is depicted in the following figure

So , Total time spent
(220 *4 ) + 22 = 902 ns

edited by
10 votes
10 votes

The size to transfer a block is always decided by source(Do not confuse yourself by looking "a block is transferred from L2 cache to L1 cache). In this case first 16 words will be transferred from main memory to L2 cache( IF nothing is mentioned, the last level cache L2 & main memory page size considered to be equal.) then only 4 words will be transferred from L2 to L1 not the whole block of L2. Now the only confusion is "This whole process of transferring block is a concurrent process or serial?".

If nothing is mentioned in the question then take serial transfer of block (in computer science we always strive for Worst case) so

1)   200ns to access main memory and 20ns to store in the L2 cache.

2)   Point (1) will happen for 4 times because of data bus = 4 words, so 16 words will be transferred in 4 times. 

3)   and after that 20ns to access or read L2 cache and 2ns to place or write it into L1 cache.

so answer would be

4*(200+20) + 20 + 2 = 902.

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