Cache size =32 KB , Block size = 32 B .
Therefore no. of cache lines = cache size / block size = 32KB/32B = 1K or 210 .
Now since we have to find out hit latency for Direct Mapped cache organization h2 :
Physical Address = 32 bits.
Block offset or Word offset = 5 ( as 25 is the block size)
Cache Line bits = 10 ( as no. of cache lines = 210)
Hence Tag bits = Physical address bits-(Block offset bits + Cache Line Bits)= 32-(10+5) =17.
Latency of comparator depends on no of tag bits as it compares the tag bits from the physical address with the output of the MUX . So here we have 17 tag bits so we need 17 bit comparator. As in question it is mentioned that for k-bit comparator latency is k/10 ns so latency of comparator in this case is 17/10 =1.7 ns
Also from h/w implementation of direct mapping we know the cache line bits (10 in this case) act as select lines for the MUX. Hence here we will need MUX which are all 210-to-1 . But in the question it is mentioned 2-to-1 MUX whose latency is essential to calculate hit latency of organization h1 that is 2-way set associative mapping and for our organization h2 that is direct mapping we have to consider MUX latency as negligible as it is not mentioned. So
Total latency = Latency of comparator(Always 1 comparator is required in Direct mapping) + Latency of MUX(negligible here)
= 1.7 ns