6.8k views

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation – the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR.

The instruction "call Rn, sub” is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$Rn \leftarrow PC + 1$;

$PC \leftarrow M[PC]$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

1. $2$
2. $3$
3. $4$
4. $5$

edited | 6.8k views
+1
What is S and T here?
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Can u explain how 3 cycles??
+14

Before looking at explanation first think --->

• First check given architecture carefully.(means check various component and their functionality )
• What are all micro-instruction required.
• How many of them could be done in parallel.

Execution cycle means OF + EX + WB together. I think keeping these things in mind proper answer could be obtained.

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Can someone tell me what GPRs is?
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General Purpose Registers
+1
Yes, general purpose register.

$MAR$ $\leftarrow$ $PC\qquad \to1$ cycle
$S$ $\leftarrow$ $PC$ (Since these two actions are independent they can be done in same cycle)
$MDR$ $\leftarrow$ $M[MAR]\qquad \to 2$nd cycle (System BUS)
$RN$ $\leftarrow$ $S +1$     (ALU Is free and the two actions are independent.) (Internal BUS)
$PC$ $\leftarrow$ $MDR\qquad \to 3$rd cycle

Therefore $3$ cycles needed.

A rough sketch:

Correct Answer: $B$

by Loyal (7.4k points)
edited
+2
In the second cycle S + 1 will be calculated but the result of increment can't be stored in the RN in the same cycle along with MDR <- M[MAR] as this will bring two different data on the bus in the same clock cycle.
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can someone elaborate?? i am unable to understand this concept.
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Even I think so. So it should be 4 cycles. I m unable to understand 3 cycles as answer
+37
@sushmita, Why 4 cycles ?

Tell me what will happen if i enable $\text{PC}_{out} \text{, MAR}_{in} \text{, and S}_{in}$ ?

Enabling  $\text{PC}_{out}$ means content of  $\text{PC}$ is available on Dta Bus, now at the same time if i enable $\text{ MAR}_{in} \text{, and S}_{in}$ that means content of $PC$ will be loaded into  $\text{MAR}$ and  $\text{S}$.

Yes we can load PC value (or any register value) to many registers in ONE cycle.

$T_0$ : $MAR \leftarrow PC \\ S \leftarrow PC$

$T_1$ : $MDR \leftarrow M[MAR] \text{ Operation on system bus (address bus)} \\ R_N \leftarrow S+1 \text{ Operation on internal bus }$

$T_2$ : $PC \leftarrow MDR$
+1
Thanx sachin. That was my doubt. i was confused about the 2 buses.
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how to  know whether the question assumes different buses?
+25

Welcome :)
Question does not assume anything, it is ALWAYS the case that system bus and internal buse needed everywhere.
System Bus: To let interact the CPU with external components. eg- Memory, I/O.
Internal Bus: To let interact the CPU with internal components. eg- Register file, ALU.

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It is mentioned that  increment operation ALU is used ,but still we need to load 1 into T,when are we loading that 1 into T ?As T is connected to bus so it must come via bus.

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@rahul

what I am getting there are not separate clock cycles for each instruction

Fetch is taking 2 clock cycles and execute takes 1 clock cycle
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@srestha ,my doubt is how 1 is loaded into the second operand of ALU while incrementing PC
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what is the best source to read about control unit design and CPU organization..?
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How can you conclusively say that ALU operation and writing to the register file happens in same cycle.This, surely depends upon the architecture.
+1

@Arjun sir,

Inhttps://gateoverflow.in/1402/gate2005-79,we have taken 2 cycles to load S and T.But in given question here,to Perform S+1 we need to load 1 into T. In which cycle we are doing this?Can someone explain this?

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yeah 3 cycle is final answer
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tucey great ho sachin paaji
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great explanation riya
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Is it a single bus organization or two bus organization?

I think it is a two bus organization
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Shouldn't MAR ← PC, and MDR ← M[MAR] be a part of the fetch cycle instead of the execution cycle as it was in the first part of the question?

+1

@ yes that the part of IF that MAR <- PC and MDR <- M[MAR] but after instruction fetch it comes to execute so what we wanted to execute we wanted to give PC value to Rn and  so we have to first access the MAR and go to Rn  so and get the value through DATA BUS to MDR that's why .......

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I think, INC  operation will be performed. So there is no need to load 1.
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nice microprocessor
0

$T_0$ : $MAR \leftarrow PC \\ S \leftarrow PC$

why two steps are required here? can we not do it in one step?

@Shaik+Masthan can u help me plz.

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@srestha

They can be and are already done in one step only.

0
How r u telling, it could be done in one step?
+2
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Why we need two steps: MDR<- M[MAR]  and PC<-MDR , when we can directly do as: PC<- M[MAR]  because both PC and memory are connected together via the data bus. why is it necessary to first transfer data from memory to MDR then from MDR to PC. I think we only need MDR when we require ALU, isnt it?

Rn <= Pc+1

Pc<= M[Pc]

The sequence of instruction take place

I Cycle : PC out  , Sin , MARin (MAR can be loaded with PCout

II Cycle: S out  , ALUincrement  , Rn in

III Cycle: MDRout  ,   PCin  (MDRout can be performed once MARin has been performed)   therefore 3 cycle required

by Boss (16.5k points)
+1
why we need to store PC value in MAR and Sin??and can we transfer PC content to Sin and MAR in same clock cycle?

Thanks
+1
Obviously we can store in same clock because once the content of PC is on bus both the registers MAR and S can activate their load input to take the data on the bus.

1)PCout ,MARin,Rin

2)MDRout ,PCin

so total 3  cycles

by Boss (31.4k points)
edited by
0

In this question PC and GPR are carried out in the ALU.

So, PC and GPR performing write operation.

"call Rn, sub” - here subroutine call is performing , which is a memory read operation

And each memory read operation takes 2 clock cycle.

Then operation is performed in ALU.

Next operation will be

Rn <= PC + 1;

PC <= M[PC];

i.e. PC is incremented which requires no clock cycle.

Next PC value will be that memory location and according to the question it is a write operation. It is the 3rd step of Fetch cycle. So, it requires 1 clock cycle.

Total 3 clock cycle

by Veteran (119k points)
0
No. Here we have an indirect memory access M[PC]. So, PC content must be moved to MAR and then memory read needs to be done and read content moved to PC. See the answer by Pooja, other stuffs like also happen but these are the important ones to get answer here.
+1
In this question us memory bus separate from the data bus shown in the diagram?
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@Arjun Sir

Pc increment is done by Add instruction or is it other instruction which increments PC by 1.If it is a add instruction then we need to load data into  i.e 1 in T register also.And if it is INC instruction then it always increment by one.But word length can be more than one?I understand that ALU will not consume any extra cycle but the way we have loaded PC into S register,the same way why havent we loaded 1 into T register?
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@Arjun sir what does this line means PC is incremented during the fetch cycle of the first word of the instruction..? And why aren't we considering for second word of this instruction in our execution cycle..?I am bit confused please clear the question to me..thanks in advance sir

$T_0$ : $MAR \leftarrow$ PC (via system bus)since MAR connected through System bus

$S \leftarrow PC$ ( via internal nus)

$T_1$ : $MDR \leftarrow M[MAR]$ {  Operation on system bus (address bus)}

$\\ R_N \leftarrow S+1 \text{ Operation on internal bus }$  {can also be done with 3rd cycle}

$T_2$ : $PC \leftarrow MDR$ ( via system bus)

Note: MAR and MDR are Connected through System bus cannot done in One Cycle.

by Veteran (63k points)
0
When doe we load 1 in to register for adding it to PC.As they have said ALU will do increment so ALU will take data from S and T register,when will we load 1 into T?
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@Prashant.
In Cycle To

"T0 : MAR←PC (via system bus)since MAR connected through System bus
S←PC ( via internal nus)"

You have done a mistake here as MAR and PC are not connected via system bus but by internal bus
We are actually performing this operation in clock T0 by putting the content of PC over internal bus and then enabling Load input of S and MAR in  same clock cycle i.e T0

Hi Guys,

Although many people have provided correct answer but It seems people want to see complete picture so just adding this answer.

In above explanation $S$ is a temporary ALU register. Notice data to and from memory comes and goes via MDR that too via separate BUS.

If provided information is not correct then please notify.

by Boss (13.7k points)
0
@Chhotu ji

can u share the source, from where u given ans?
0

can u share the source, from where u given ans?

@srestha ji,

This answer is not available anywhere. I derived it based on whatever is mentioned in question and standard text book.

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very nice explanation...but i have one doubt

the pc will increment to 2 in instruction fetch phase  or it will increment to 2 after instruction decode phase?
0

Great solution considering the book Hamacher et al.

A correction by the way, the register Rnin takes input from MARin

1 cycle: Pc out->S in, MAR in,

2 cycle: S out => ALU increment

3 cycle:  MBR out => Pc in

so it must be 3 cycle
by Boss (10.1k points)

3 clock cycles

by Junior (817 points)
reshown