GATE CSE 2005 | Question: 80

Question

Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction "call Rn, sub” is a two word instruction. Assuming that $\text{PC}$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$\text{Rn} \leftarrow \text{PC} + 1$;

$\text{PC} \leftarrow \text{M[PC]}$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

• A. $2$
• B. $3$
• C. $4$
• D. $5$

Comments

@srestha

Does they asked for it?

Even if they didn't ask then how are you planning to do it ?

They asked to show the execute cycle of "call Rn, sub”.

And that maynot even require PC,GPR,S or T(as shown in diagram) , those thing when this subroutine is calling.

Please, can you write down the steps for $"call\ Rn,sub"$ which you think is valid.

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@Kushagra गुप्ता

I think like this.

Though the question is asking for execution cycle, but in this subroutine call instruction, there is nothing to execute. Like add, subtract or branching like operation. 

So, what is need to be perform here, nothing but Fetch cycle.

Steps are

1) First Fetch address of the subroutine. Put MAR value in PC.

2)Increment PC value. As it is a memory read operation, wait for Memory Function Complete Signal(WMFC).

3) Fetch data By MDR and put it in IR.

Let me know, if it is correct.

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someone please provide video lecture link related to this concept

Answer 1

In this question PC and GPR are carried out in the ALU.

So, PC and GPR performing write operation.

"call Rn, sub” - here subroutine call is performing , which is a memory read operation

And each memory read operation takes 2 clock cycle.

Then operation is performed in ALU.

$1)PC_{out},MAR_{in},Read,IncPC$

$2)WMFC$

$3)R_{2out},R_{3out},SelectA,SUB,R_{1in},END$

First two are FETCH cycle and 3rd one executing SUB instruction,i.e. EXECUTE cycle

Total 3 clock cycle

Comments

No. Here we have an indirect memory access M[PC]. So, PC content must be moved to MAR and then memory read needs to be done and read content moved to PC. See the answer by Pooja, other stuffs like also happen but these are the important ones to get answer here.

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In this question us memory bus separate from the data bus shown in the diagram?

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@Arjun Sir

Pc increment is done by Add instruction or is it other instruction which increments PC by 1.If it is a add instruction then we need to load data into  i.e 1 in T register also.And if it is INC instruction then it always increment by one.But word length can be more than one?I understand that ALU will not consume any extra cycle but the way we have loaded PC into S register,the same way why havent we loaded 1 into T register?

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@Arjun sir what does this line means PC is incremented during the fetch cycle of the first word of the instruction..? And why aren't we considering for second word of this instruction in our execution cycle..?I am bit confused please clear the question to me..thanks in advance sir

Answer 2

$T_0$ : $ MAR \leftarrow$ PC (via system bus)since MAR connected through System bus  

          $ S \leftarrow PC$ ( via internal nus)

$T_1$ : $ MDR \leftarrow M[MAR]$ {  Operation on system bus (address bus)}

$\\ R_N  \leftarrow S+1  \text{  Operation on internal bus }$  {can also be done with 3rd cycle}

$T_2$ : $PC \leftarrow MDR$ ( via system bus)

Note: MAR and MDR are Connected through System bus cannot done in One Cycle.

Comments

When doe we load 1 in to register for adding it to PC.As they have said ALU will do increment so ALU will take data from S and T register,when will we load 1 into T?

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@Prashant.
In Cycle To

"T0 : MAR←PC (via system bus)since MAR connected through System bus  
    S←PC ( via internal nus)"

You have done a mistake here as MAR and PC are not connected via system bus but by internal bus
We are actually performing this operation in clock T0 by putting the content of PC over internal bus and then enabling Load input of S and MAR in  same clock cycle i.e T0

Answer 3

3 clock cycles

Answer 4

1 cycle: Pc out->S in, MAR in,

2 cycle: S out => ALU increment

3 cycle:  MBR out => Pc in

so it must be 3 cycle