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Consider the following data path of a $\text{CPU}.$

The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the $\text{ALU}.$ Two clock cycles are needed for memory read operation – the first one for loading address in the $\text{MAR}$ and the next one for loading data from the memory bus into the $\text{MDR}.$

The instruction "call Rn, sub” is a two word instruction. Assuming that $\text{PC}$ is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

$\text{Rn} \leftarrow \text{PC} + 1$;

$\text{PC} \leftarrow \text{M[PC]}$;

The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:

  1. $2$
  2. $3$
  3. $4$
  4. $5$
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Best answer
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88 votes
  • $\text{MAR} \leftarrow  \text{PC}\qquad \to1$ cycle
  • $S \leftarrow \text{PC}$ (Since these two actions are independent they can be done in same cycle)
  • $\text{MDR} \leftarrow \text{M[MAR]}\qquad \to 2^{nd}$ cycle (System BUS)
  • $\text{Rn} \leftarrow S +1$ $(\text{ALU}$ Is free and the two actions are independent.) (Internal BUS)
  • $\text{PC} \leftarrow \text{MDR}\qquad \to 3$rd cycle

Therefore $3$ cycles needed.

A rough sketch:

Correct Answer: B

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8 votes

Rn <= Pc+1

Pc<= M[Pc]

The sequence of instruction take place 

 

I Cycle : PC out  , Sin , MARin (MAR can be loaded with PCout

II Cycle: S out  , ALUincrement  , Rn in

III Cycle: MDRout  ,   PCin  (MDRout can be performed once MARin has been performed)   therefore 3 cycle required

 
6 votes
6 votes

Hi Guys,

Although many people have provided correct answer but It seems people want to see complete picture so just adding this answer.

So Answer is B part.

In above explanation $S$ is a temporary ALU register. Notice data to and from memory comes and goes via MDR that too via separate BUS.

If provided information is not correct then please notify.

5 votes
5 votes

1)PCout ,MARin,Rin

2)MDRout ,PCin

2 cycles to read

so total 3  cycles

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Answer:

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