edited by
19,516 views
59 votes
59 votes

Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$

\begin{array}{|l|l|c|} \hline \text {Instruction}  &  \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV $R_1,5000$} 
& \text{$R1$} \leftarrow  \text{Memory$[5000]$}& \text{$2$} \\\hline\text{MOV $R_2(R_1)$} & \text{$R2$} \leftarrow  \text{Memory$[(R_1)]$}& \text{$1$} \\\hline \text{ADD $R_2,R_3$} & \text{$R_2$} \leftarrow  \text{$R_2 + R_3$} & \text{$1$} \\\hline \text{MOV $6000,R_2$} & \text{Memory$[6000]$} \leftarrow  \text{$R_2$} & \text{$2$} \\\hline \text{Halt} & \text{Machine Halts} & \text{$1$} \\\hline \end{array}

Let the clock cycles required for various operations be as follows:

\begin{array}{|l|l|} \hline \text {Register to/from memory transfer}  &  \text{3 clock cycles } \\\hline  \text {ADD with both operands in register}  &  \text{1 clock cycles } \\\hline \text {Instruction fetch and decode}  &  \text{2 clock cycles }\\\hline \end{array}

The total number of clock cycles required to execute the program is

  1. $29$
  2. $24$
  3. $23$
  4. $20$
edited by

4 Answers

Best answer
125 votes
125 votes

B.  $24 \text{ cycles}$

$$\begin{array}{|l|c|c|} \hline \text {Instruction}  &  \text{Size }& \text{Fetch and Decode + Execute} \\\hline \text{MOV} & \text{$2$} & \text{$2$} \times \text{$2 + 3 = 7$} \\\hline  \text{MOV} & \text{$1$} & \text{$2$} \times \text{$1 + 3 = 5$} \\\hline  \text{ADD} & \text{$1$} & \text{$2$} \times \text{$1 + 1 = 3$} \\\hline \text{MOV} & \text{$2$} & \text{$2$} \times \text{$2 + 3 = 7$} \\\hline \text{HALT} & \text{$1$} & \text{$2$} \times \text{$1 + 0 = 2$} \\\hline   & \text{Total} & \text{$24 $ Cycles} \\\hline \end{array}$$

edited by
38 votes
38 votes
Each instructions requires fetch and decode

So total instructions size is 7 words

Number of cycles = 7*2=14 cycles

Now in addition to that

Move     R1,5000 3 cycles for register /to memory transfer

Move     R2,(R1)  3 cycles

Add        R2,R3    1 cycle ALU

Move     6000,R2  3 cycle

Additional 10 cycle

Total = 14+10=24 cycles
edited by
8 votes
8 votes

The clock cycles are per block; if an instruction size is 2 then it requires twice no. of clock cycles.

Instruction no.       size                                              no. of clock cycles
1                                2                                                                       3*2+2
2                                1                                                                       1*3+2
3                                1(add only)                                                      1
4                                2                                                                       3*2+2
5                                1                                                                       2(fetch and decode)
                                Total                                                                  24

  So answer is (B)

2 votes
2 votes
$3+3+1+3+7(2)=24$

Why the Instruction Fetch and Decode is counted 7 times when the number of instructions are 5?

Because the largest unit of memory that can be transferred to and from it, in a single operation is the word size. Since there are 7 words in total, to fetch them we need to devote 7 separate operations, and each such operation would take 2 clock cycles (given)
Answer:

Related questions

70 votes
70 votes
4 answers
1
Kathleen asked Sep 18, 2014
28,862 views
Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$ $$\begin{array}{|l|l|c|} \hline \text {Instruction} & \t...
35 votes
35 votes
3 answers
2
52 votes
52 votes
10 answers
3