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+45 votes

Consider the following program segment for a hypothetical CPU having three user registers $R_1, R_2$ and $R_3.$

\begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV $R_1,5000$}

& \text{$R1$} \leftarrow \text{Memory$[5000]$}& \text{$2$} \\\hline\text{MOV $R_2(R_1)$} & \text{$R2$} \leftarrow \text{Memory$[(R_1)]$}& \text{$1$} \\\hline \text{ADD $R_2,R_3$} & \text{$R_2$} \leftarrow \text{$R_2 + R_3$} & \text{$1$} \\\hline \text{MOV $6000,R_2$} & \text{Memory$[6000]$} \leftarrow \text{$R_2$} & \text{$2$} \\\hline \text{Halt} & \text{Machine Halts} & \text{$1$} \\\hline \end{array}

Let the clock cycles required for various operations be as follows:

\begin{array}{|l|l|} \hline \text {Register to/from memory transfer} & \text{3 clock cycles } \\\hline \text {ADD with both operands in register} & \text{1 clock cycles } \\\hline \text {Instruction fetch and decode} & \text{2 clock cycles }\\\hline \end{array}

The total number of clock cycles required to execute the program is

- $29$
- $24$
- $23$
- $20$

+83 votes

Best answer

**B. ** $24 \text{ cycles}$

$$\begin{array}{|l|c|c|} \hline \text {Instruction} & \text{Size }& \text{Fetch and Decode + Execute} \\\hline \text{MOV} & \text{$2$} & \text{$2$} \times \text{$2 + 3 = 7$} \\\hline \text{MOV} & \text{$1$} & \text{$2$} \times \text{$1 + 3 = 5$} \\\hline \text{ADD} & \text{$1$} & \text{$2$} \times \text{$1 + 1 = 3$} \\\hline \text{MOV} & \text{$2$} & \text{$2$} \times \text{$2 + 3 = 7$} \\\hline \text{HALT} & \text{$1$} & \text{$2$} \times \text{$1 + 0 = 2$} \\\hline & \text{Total} & \text{$24 $ Cycles} \\\hline \end{array}$$

+1

One very sily clearification i need here is : we have not considered operand fetch for ADD instruction because we have already moved it to register R1, right? when to consider operand fetch seperaely in any question? will it be given directly in question?

+1

Operand fetch is not required if the content is already in registers, because processor operates directly on the registers. Think this way, where does the processor is going to keep the operands after fetching it from the registers. Instructions which use registers only can operate directly on the registers itself.

0

Why we are considering it as Non pipeline architecture as no. of clock cycles in pipeline will be less.

0

Indirect addressing is present in second instruction, so there should be two memory references to get the data stored in the memory. therefore answer should be 27.

please confirm!

please confirm!

+1

@shreys02 In Indirect addressing also we consider only one register to/from memory transfer so that will take only 3 cycles.

+23 votes

Each instructions requires fetch and decode

So total instructions size is 7 words

Number of cycles = 7*2=14 cycles

Now in addition to that

Move R1,5000 3 cycles for register /to memory transfer

Move R2,(R1) 3 cycles

Add R2,R3 1 cycle ALU

Move 6000,R2 3 cycle

Additional 10 cycle

Total = 14+10=24 cycles

So total instructions size is 7 words

Number of cycles = 7*2=14 cycles

Now in addition to that

Move R1,5000 3 cycles for register /to memory transfer

Move R2,(R1) 3 cycles

Add R2,R3 1 cycle ALU

Move 6000,R2 3 cycle

Additional 10 cycle

Total = 14+10=24 cycles

+8 votes

The clock cycles are per block; if an instruction size is 2 then it requires twice no. of clock cycles.

Instruction no. size no. of clock cycles |

1 2 3*2+2 |

2 1 1*3+2 |

3 1(add only) 1 |

4 2 3*2+2 |

5 1 2(fetch and decode) |

Total 24 |

So answer is **(B)**

+1 vote

$3+3+1+3+7(2)=24$

Why the Instruction Fetch and Decode is counted 7 times when the number of instructions are 5?

Because the largest unit of memory that can be transferred to and from it, in a single operation is the word size. Since there are 7 words in total, to fetch them we need to devote 7 separate operations, and each such operation would take 2 clock cycles (given)

Why the Instruction Fetch and Decode is counted 7 times when the number of instructions are 5?

Because the largest unit of memory that can be transferred to and from it, in a single operation is the word size. Since there are 7 words in total, to fetch them we need to devote 7 separate operations, and each such operation would take 2 clock cycles (given)

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