edited by
23,663 views
83 votes
83 votes

A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most significant bits of the virtual address are used as index into the first level page table while the next $10$ bits are used as index into the second level page table. The $12$ least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are $4$ bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of $\text{96%}$. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of $\text{90%}$. Main memory access time is $10$ ns, cache access time is $1$ ns, and TLB access time is also $1$ ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address $0x00000000$, two contiguous data pages starting at virtual address $0x00400000$, and a stack page starting at virtual address $0xFFFFF000$. The amount of memory required for storing the page tables of this process is

  1. $\text{8 KB}$
  2. $\text{12 KB}$
  3. $\text{16 KB}$
  4. $\text{20 KB}$
edited by

6 Answers

7 votes
7 votes

.

PO : Page Offset

PTi : Inner Page Table

PTo: Outer Page Table

 

 

 

 

 

 

–3 votes
–3 votes

Since page offset is of size 12 bit and memory is byte addressable. So we can say that page size=2^12 Byte=4KB.

Now process needs 5 pages of page no.

0x 00000 and 0x 00001 for code,

0x 00400 and 0x 00401 for data, and

0x FFFFF for stack.

Now for mapping above pages in to frames we need one outer page table and two inner page tables(One  inner page table needed for mapping all these four pages

0x 00000, 0x 00001, 0x 00400 and 0x 00401, and another inner page needed for mapping 0x FFFFF).

So, total no of page table needed for above process is 3.

The amount of memory required for storing the page tables of this process is 3*4KB = 12KB 

edited by
Answer:

Related questions

55 votes
55 votes
7 answers
3
go_editor asked Apr 24, 2016
14,696 views
Suppose we want to synchronize two concurrent processes $P$ and $Q$ using binary semaphores $S$ and $T$. The code for the processes $P$ and $Q$ is shown below.$$\begin{ar...