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Which logic gate is used to detect overflow in 2's compliment arithmetic?

1. OR gate
2. AND gate
3. NAND gate
4. XOR gate
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Overflow detection circuit for 2's complement addition

One way to detect it is to XOR the carry in and the carry out.

1. If the sum of two positive numbers yields a negative result, the sum has overflowed.
2. If the sum of two negative numbers yields a positive result, the sum has overflowed.
3. Otherwise, the sum has not overflowed.

It is important to note the overflow and carry out can each occur without the other. In unsigned numbers, carry out is equivalent to overflow. In two's complement, carry out tells you nothing about overflow.

The reason for the rules is that overflow in two's complement occurs, not when a bit is carried out out of the left column, but when one is carried into it. That is, when there is a carry into the sign. The rules detect this error by examining the sign of the result. A negative and positive added together cannot overflow, because the sum is between the addends. Since both of the addends fit within the allowable range of numbers, and their sum is between them, it must fit as well.

by Boss (45.4k points)
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Xor gate is used .
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