Why option 1 and 2 are correct
If the the caches are not write through, we can have a imbalance between the LRU counter in the L1 and L2 caches. leading to a situation where the inclusion property will fail eventually. Hence every HIT in L1, must propogate to L2 also, in order to maintain consistency in the LRU counter.
The video given below displays a good example of this problem, when write through cache are not used.
Why option 4 is also correct
The size of L1 and L2 caches can be equal, or L2 can be greater.
case 1 (If they are equal or L2 is greater): This part is quiet self explanatory, in this case we are sure to have atleast as many entries in L1 as L2, also L2 can have extra lines which does not affect our inclusion property.
case 2 (If L1 is greater than L2): Lets say L1=10 lines and L2=2 lines, if block 0, 1 are accessed, they lead to compulsary misses and are now available in L1 as well as L2.
Now lets say we access 3,
in L2 cache, we must have it replace atleast one out of 0, 1, and due to greater size of L1 we may not necessarily map 3 to existing position, when this occurs we will have violated our inclusion property.
Hence I believe the answer to be (c)
Hello Everyone, this is my very first post, so i'm sorry If my explanation is not explained as well as it should be.