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Which of the following are NOT true in a pipelined processor?

  1. Bypassing can handle all RAW hazards
  2. Register renaming can eliminate all register carried WAR hazards
  3. Control hazard penalties can be eliminated by dynamic branch prediction
  1. I and II only
  2. I and III only
  3. II and III only 
  4. I, II and III
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Here bypassing doesn't mean from MA to execute stage?

bypassing only means the output of the execute stage is fed to the input of execute stage

Dileep kumar M 6


This link states:

 Register renaming won't help with this problem, because the space of visible memory locations is enormous compared to the number of available registers. 

So, this means, register renaming is NOT able to eliminate ALL possible WAR/WAW hazards, right? Because then we use a queue for stores as a solution to this problem. But register renaming still fails here, right? So, is it still true that register renaming can eliminate ALL WAR hazards? Please respond ASAP. :)

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Helpful videos on Dynamic branch prediction:

Video 1

Video 2

Video 3

In Load/store instruction, why there is no split phase concept, I mean MA in 1st half & EX in 2nd half ??

then both state can be overlapped & no stalls.
Both MA as well as EX are not stages which can finish in a half cycle. For example, EX can involve an Adder being activated and only once this adder output is generated, MA can be performed. Register file write and read can be done in a single cycle because data is readily available here.
thanks :)
Arjun sir, I have seen some pyqs where there was Ex-OF stage split phasing.

Is it the case that Ex-Mem stage together cant have split phasing because no stage can have split phasing with Mem stage as it cant finish up in half a clock cycle?

awesome link to help you out !! Microsoft PowerPoint - arch12-handout.ppt


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1 Answer

81 votes
Best answer
(B) I and III

I - False    Bypassing can't handle all RAW hazard, consider when any instruction depends on the result of LOAD instruction, now LOAD updates register value at Memory Access Stage (MA), so data will not be available directly on Execute stage.

II - True, register renaming can eliminate all WAR Hazard.

III- False, It cannot completely eliminate, though it can reduce Control Hazard Penalties
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Thats correct. But dynamic branch prediction can eliminate almost 99% of control hazards :)
Didn't knew Arjun sir that optimizations have improved so much :)
My team lead is the world champion on branch prediction competition :) He owns the best branch predictor.
@Arjun Sir:Plz give a scenario where bypassing can't handle a RAW hazard...
when there are three instructions and 3rd instruction reads the values written by first instruction.

also when there are 2 instructions with RAW dependency and first instruction is a load/store instruction.
But bypassing can eliminate RAW as operand forwarding can be done from memory stage too by adding another input at mux before input to ALU
@Arjun sir any refrence for branch prediction
because I have read somewhere that delayed branch prediction can also be used to remove hazards
sir i think answer should be 1 st only as control hazards can be elimineted by dynamic branch pridiction but as option is not given thats why I and 3 rd right ?
Register renaming can handle all WAR hazards?Can you share some reference for this point?It didnt find this point in my book.And on internet they are saying it is not possible to completely remove WAR with register renaming
not refrence but i have studied as if their is WAR hazards like R1<-- r2 + r3 & r2 <--- r3 + r5 we can rename second R2 to resolve this conflict so depandency get resloved

If more no of physical register (i.e. sufficient to use in multiple instructions) is not available, can register renaming solve WAR and WAW always?


rahul sharma 5 Register renaming can handle all WAR hazards?  is it possible to completely remove WAR with register renaming ..?

yeah it as possible to remove completely WAR and  WAW hazards the only RAW hazards cant be removed completely

@Arjun sir, I think answer should be A) because

statement III) is saying  Control hazard penalties can be eliminated by dynamic branch prediction it is not saying that It will always eliminate Control hazards., as you also said that 99% time it works so it can, but not always.(1%)---->so TRUE

statement II) suppose we have limited number of registers but our programme is so large that required registers for renaming are much larger. than register renaming will fail here.I don't know this scenario is practically  possible or not but theoretically It might be fail.

Register renaming can not only eliminate WAR hazard but also WAW hazard ...
always? @vicky

reena_kandari yes 

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we have limited number of registers but our program is so large that required registers for renaming are much larger. than register renaming will fail here.

First of all good point. But we do not execute entire program in one shot. For example if we have 5 stage in pipe line then only 5 different instruction can execute in parallel that to in different stage of pipe line. Now Based on processor instruction set it could be calculated in worst case how much register could be used.  So if  processor has that many number of register then OK otherwise Renaming it self could not be done and Hazard may come. 

@Vicky rix ji @reena_kandari and @VS ji what is your opinion ?


@chhotu, you might be correct but  this is topic of CO, so we can't say what is exactly used in Architecture.There may be many other things going while CPU is executing a set of instructions.CPU may be executing many other programs concurrently..or we can say lots of instruction concurrently and if we use same finite set of registers Then I think it will be a overhead of using those same registers for renaming(due to lots of context switching and load/store instruction back to memory)

read this,

From a computer architecture point of view, an additional problem for write-after-read hazards is dealing with load and store operations to main memory. Register renaming won't help with this problem

for 1st option    , after load operation in MA cycle can't we pass the the value to execution cycle by operand forwarding through buffer  ??   what is the problem here in removing RAW HAZARD . plz explain
yes I) could be true
please don't copy paste from other sites :P

@Prateeksha Keshari  operand forwarding not possible for the case mentioned by you but in this question operand forwarding is possible from MA to EX. Please explain the scenario here ... Thank you


Branch prediction, frequency of missprediction near to 0 in nASA7.

Still its not 100%

Thats the benchmark in 2019

Reference: Advanced Computer Architecture Hennessy and Patterson.


Also good READ:


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