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+26 votes

Which of the following are NOT true in a pipelined processor?

  1. Bypassing can handle all RAW hazards
  2. Register renaming can eliminate all register carried WAR hazards
  3. Control hazard penalties can be eliminated by dynamic branch prediction
  1. I and II only
  2. I and III only
  3. II and III only 
  4. I, II and III
asked in CO & Architecture by Veteran (59.5k points)
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Here bypassing doesn't mean from MA to execute stage?

bypassing only means the output of the execute stage is fed to the input of execute stage

Dileep kumar M 6

1 Answer

+45 votes
Best answer
(B) I and III

I - False    Bypassing can't handle all RAW hazard, consider when any instruction depends on the result of LOAD instruction, now LOAD updates register value at Memory Access Stage (MA), so data will not be available directly on Execute stage.

II - True, register renaming can eliminate all WAR Hazard.

III- False, It cannot completely eliminate, though it can reduce Control Hazard Penalties
answered by Active (2.2k points)
selected by
yeah it as possible to remove completely WAR and  WAW hazards the only RAW hazards cant be removed completely

@Arjun sir, I think answer should be A) because

statement III) is saying  Control hazard penalties can be eliminated by dynamic branch prediction it is not saying that It will always eliminate Control hazards., as you also said that 99% time it works so it can, but not always.(1%)---->so TRUE

statement II) suppose we have limited number of registers but our programme is so large that required registers for renaming are much larger. than register renaming will fail here.I don't know this scenario is practically  possible or not but theoretically It might be fail.

Register renaming can not only eliminate WAR hazard but also WAW hazard ...
always? @vicky

reena_kandari yes 



we have limited number of registers but our program is so large that required registers for renaming are much larger. than register renaming will fail here.

First of all good point. But we do not execute entire program in one shot. For example if we have 5 stage in pipe line then only 5 different instruction can execute in parallel that to in different stage of pipe line. Now Based on processor instruction set it could be calculated in worst case how much register could be used.  So if  processor has that many number of register then OK otherwise Renaming it self could not be done and Hazard may come. 

@Vicky rix ji @reena_kandari and @VS ji what is your opinion ?


@chhotu, you might be correct but  this is topic of CO, so we can't say what is exactly used in Architecture.There may be many other things going while CPU is executing a set of instructions.CPU may be executing many other programs concurrently..or we can say lots of instruction concurrently and if we use same finite set of registers Then I think it will be a overhead of using those same registers for renaming(due to lots of context switching and load/store instruction back to memory)

read this,

From a computer architecture point of view, an additional problem for write-after-read hazards is dealing with load and store operations to main memory. Register renaming won't help with this problem

for 1st option    , after load operation in MA cycle can't we pass the the value to execution cycle by operand forwarding through buffer  ??   what is the problem here in removing RAW HAZARD . plz explain
yes I) could be true

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