# GATE2008-38

5.8k views

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:

1. before effective address calculation has started

3. after effective address calculation has completed

4. after data cache lookup has completed

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In a system without virtual memory , the EA will be either a main memory address or a register.

In a virtual memory system , the EA is a virtual address or a register.
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TLB stores only page table of large size program(Programs which are unable to fit in main memory). so after effective address calculation the given address will be reached using help of the page table of that program stored in TLB. Since virtual program is large in size so page table is also large & do not get fit in one page so multi-level paging. TLB decreases the access time to search in multi-level page table because it provides superfast memory access.

Effective address is the address after applying the addressing mode like indexed, immediate etc. But this resulting address is still the virtual address, the physical address is invisible to the CPU and will be given only by the MMU when given the corresponding virtual address. Virtual address is given for TLB look up. TLB -Translation Lookaside Buffer, here Lookaside means during Address translation (from Virtual to Physical). But virtual address must be there before we look into TLB.

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Here the answer given is B. Is C right or B?
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Where is B given? C is the answer.
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That is wrong explanation. they are explaining for physical address resolution and not for effective address calculation.
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Thank you sir.
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in case of indirect addressing mode.the flow will  be

[data from address field ] -> memory access-> TLB ->actual frame address ->data in that memory location -> back to processor->now this data is my effective address.

sir,so i think answer should be B.

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I suppose the question is clear that it is referring to the TLB lookup for a given memory access.
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Sir the pdf you have mentioned says "instruction TLB" to be accessed before effective address calculation not the "data TLB". And the data cache access is specified after the calculation of the effective address.

Sir what is the concept here? Where to get theory about such topics?

Plzz help.
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If indirect addressing mode is used then answer should be b) . Also as earliest is asked, I think we can assume indirect addressing. @Arjun Sir.
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CPU generates a virtual address (for doing something with an instruction)

That effective address when passes through the MMU, we get physical address.

While studying operating systems, we read that the virtual address is given to the TLB to fetch the corresponding frame number. But that is not strictly true, as we have to maintain certain level of abstractions to stay in context. In the Operand Fetch Phase (studied in CO&A), the Virtual Address is translated to Effective Address, and in actuality that is given to the TLB.
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Yes, Answer will be option C, because EA(logical address) calculation means knowing the location of operand. There are different addressing mode available where EA present Directly or Indirectly in instruction's address field. By adding,subtracting(for ex. Relative mode), incrementing, etc, we get to know the EA. This is what a EA calculation, not the conversion of Logical(EA) to physical address is EA calculation.
C as only after the calculation of Virtual address you can look up in the TLB

in case of indirect addressing mode.the flow will  be

[data from address field ] -> memory access-> TLB ->actual frame address ->data in that memory location -> back to processor->now this data is my effective address.

sir,so i think answer should be B.

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Seems reasonable....
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Effective = logical
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Explanation: When we calculate effective address, first of all we access TLB to access the Frame number.

Logical address generated by CPU breaks in two parts : page number and page offset, for faster accessing of data we place some page table entries in a small hardware TLB whose access time is same as cache memory. So initially when page no. is mapped to find the corresponding frame no., first it is look up in TLB and then in page-table (in case if TLB miss).

During effective address calculation TLB is accessed.

So (B) is correct option.

TLB is a mini page table and it contains the frequently accessed page table entries. Since logical address is effective address, only after we calculate what is the effective address we can access the TLB. Hence option C is the correct answer.

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Yes this seems correct. My reason would be that during eff address calculation logical address needs to be converted to physical addresses. For this conversion tlb would first come into picture. Hence it would be during the effective address calculation only....is this correct???
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@Arjun Sir which is correct Bor C?
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an effective address is Virtual address and after Virtual address calculation we look into TLB. So option C is correct.

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@Bikram sir sir

it means after calculation of effective/logical address we look into TLB to check whether  data is present or not

this is the reason for C option
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@set2018

Yes correct

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