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Consider a 8 million word physical memory and 256 block cache, both partitioned into 64 word blocks.

Find the tag memory required for cache memory for the following mapping techniques:

a) Direct

b) Associative

c) 4-way Set Associative

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From question it is clear that we are using a physically addressed (physical indexing and physical tag) cache.

Question is asking for memory requirement for different cache implementations and this include the cache memory size + tag memory size.

Physical address: 28 bit ; Cache Blocks : 256 : 8 bit ;  Word Offset : 64 : 6 bit

Direct  : TAG : CacheLines : Offset  ::  14 : 8 :6

Associative : TAG : Offset :: 22:6

4-Way Set Associative : TAG : Cache Set : Offset :: 16:6:6

Cache Capacity : Cache Size ( A ) + TAG Memory (B)

(A) : Cache Size  = No of cache Lines * Block Size = 256 * 64 = 2^16 word  = 16384 is same for all the schemes.

Direct:

(B) : TAG Memory = Bits for TAG * Cache Lines = 14 * 256 = 3584 bits

Cache Capacity = (A) + (B)

Associative:

(B) : TAG Memory = Bits for TAG * Cache Lines = 22 * 256  = 5632 bits

Cache Capacity = (A) + (B)

4-way Set Associative:

(B) : TAG Memory = Bits for TAG * Cache Lines = 16 * 256 bits

Cache Capacity = (A) + (B)

We cannot get the total memory required for cache implementation as we do not know the word size.

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