From question it is clear that we are using a physically addressed (physical indexing and physical tag) cache.
Question is asking for memory requirement for different cache implementations and this include the cache memory size + tag memory size.
Physical address: 28 bit ; Cache Blocks : 256 : 8 bit ; Word Offset : 64 : 6 bit
Direct : TAG : CacheLines : Offset :: 14 : 8 :6
Associative : TAG : Offset :: 22:6
4-Way Set Associative : TAG : Cache Set : Offset :: 16:6:6
Cache Capacity : Cache Size ( A ) + TAG Memory (B)
(A) : Cache Size = No of cache Lines * Block Size = 256 * 64 = 2^16 word = 16384 is same for all the schemes.
Direct:
(B) : TAG Memory = Bits for TAG * Cache Lines = 14 * 256 = 3584 bits
Cache Capacity = (A) + (B)
Associative:
(B) : TAG Memory = Bits for TAG * Cache Lines = 22 * 256 = 5632 bits
Cache Capacity = (A) + (B)
4-way Set Associative:
(B) : TAG Memory = Bits for TAG * Cache Lines = 16 * 256 bits
Cache Capacity = (A) + (B)
We cannot get the total memory required for cache implementation as we do not know the word size.