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ISRO2009-39 , GATE2008-IT_15

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A processor that has carry, overflow and sign flag bits as part of its program status word (PSW) performs addition of the following two $2’s$ complement numbers $01001101$ and $11101001.$  After the execution of this addition operation, the status of the carry, overflow and sign flags, respectively will be

  1. $1, 1, 0$
  2. $1, 0, 0$
  3. $0, 1, 0$
  4. $1, 0, 1$
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1  1

     01001101

   +11101001

  -----------------

 1 00110110

carry flag=1        (extra bit out of msb)

overflow flag=0 (since both in carry out carry =1 and it is addition of -ve and +ve number so                                     overflow should be equals to 0)

                        (overflow bit =0 if both in carry out carry =0 or1 / addition of -ve and +ve number

                          & overflow bit =1 if either one of them is 1 and other is 0)

Sign bit =0  (since msb bit is 0)

therefore option B.
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