ISI2011-PCB-CS-6a

Question

Assume a machine has $4$ registers (one of which is the accumulator $A$) and the following instruction set.

• $\text{LOAD}$ and $\text{STORE}$ are indirect memory operations that load and store, using the address stored in the given register operand. Thus, $\text{LOAD R}$ loads the contents of $\text{memory}[R]$ into $A$, and $\text{STORE R}$ stores the contents of $A$ in $\text{memory[R]}$.
• $MOV$ copies any register into any other register.
• $ADD$ and $SUB$ operate on the accumulator and one other register, such that $A = A \text{ op } R$.
• $LDC$ stores a given $7$-bit constant in the accumulator.
• $BRA$, $BZ$, and $BNE$ are branch instructions, each taking a $5$ – bit offset.

Design an instruction encoding scheme that allows each of the above instructions (along with operands) to be encoded in $8$ bits.

Answer 1

As machine has $4$ registers, $\log_2 4 = 2-bits$ are required for register identification.

we have 8 bits for an instruction.

given that LDC has a immediate operand of size 7 bits ==> we left with 1 bit to identify this instruction

∴ assign 0 or 1 to it and fix it ! ( i preferred 0 and i am filling the bits from Right to Left, i.e., MSB → LSB )

For remaining type of instructions 1$^{st}$ bit is fixed to 1.

 

BRA,BZ, and BNE instructions takes 5 bits as offset.

to uniquely identified these operations we need atleast 2 bits, but there are more combinations with them, So remaining were used to identify some other instructions.

So, Fix the 2$^{nd}$ and 3$^{rd}$ bits as

00 ---> for BRA

01 ---> for BZ

10 ---> BNE

11 ---> to continue decode remaining instructions

 

MOV copies any register into any other register.  ====> instruction like MOV R$_i$,R$_j$

for this instructions operands takes 2+2=4 Bits, already first 3 bits are fixed, Keep 0 at 4$^{th}$ bit from MSB.

 

Now remaining option is Keep 1 at 4$^{th}$ bit from MSB.

Remaining instructions are

Load R$_i$

Store R$_i$

Add R$_i$

Sub R$_i$

all these instructions are take 2 bits for operand ==> Reserve at LSB bits.

remaining size we have = first 4 bits fixed from MSB and Last 2 bits fixed ==> in the middle, we have 2 bits remaining

we have 4 instructions ( i.e., Load,Store,Add,Sub ), which requires 2 Bits ==> fix them

00 ---> ADD

01 ---> SUB

10 ---> LOAD

11 ---> STORE

 

 

The instruction format is: 

Comments

Great Answer.

Answer 2

if the instruction format is of fixed type....such that 3 bits for opcode 5 bits for operand than  instruction encoding scheme:

000=  add

001= sub

010= mov

011 = load

100 = store

101 = bra

110 = bz

111= bne

but we can not represent LDC which requires 1 bit opcode 7 bits constant....

if we go for 4 bit opcode format than branch instruction condition fails because it requires..5 bits for offset..

i think may be question is wrong////