Execution Rate of pipeline

Question

Consider a non- pipelined machine with 10 ns clock cycle. It uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Let due to clock skew and pipelining setup, the machine adds 1 ns of overhead to the clock. How much speed in instruction execution rate will we gain from pipelining?

Answer 1

First of all average cycles for one instruction :  $4*0.4 \ + 4*0.2 \ + 5*0.4 \ = 4.4$ cycles.

Without using pipeline processor one instruction takes = $10ns \ *4.4 = 44 ns$ = t_n

With Pipeline processor considering CPI as one ( because questions does not provide any other stalls or delay) pipeline clock speed = 10ns + overhead = 11ns = t_p

SpeedUp = $\frac{44}{11} = 4$

Ref : https://www.udacity.com/wiki/hpca/problem-set-solutions/pipelining/problem6a

Comments

Virtually same as this one

---

can you explain what does clock skew means?

Answer 2

For executing one instruction Tavg=0.4*4+0.2*4+0.4*5=44

Twp=44;

Tp=Tc+Toverhead=10+1=11ns

Now;

Speedup=Twp/Tp=44/11=4

Answer 3

speedup=Time(non-pipelined)/Time(pipelined)

Time(non-pipelined)=10ns 

Time(pipelined)=0.4*4+0.2*4+0.4*5=4.4 ns (plus 1ns overhead)=5.4ns

speed up= 10/5.4=1.85