Consider a non- pipelined machine with 10 ns clock cycle. It uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Let due to clock skew and pipelining setup, the machine adds 1 ns of overhead to the clock. How much speed in instruction execution rate will we gain from pipelining?