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A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

  • Bits $30-31$ are used to index into the first level page table.
  • Bits $21-29$ are used to index into the 2nd level page table.
  • Bits $12-20$ are used to index into the 3rd level page table.
  • Bits $0-11$ are used as offset within the page.

The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively

  1. $\text{20,20,20}$
  2. $\text{24,24,24}$
  3. $\text{24,24,20}$
  4. $\text{25,25,24}$
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Page table is stored in main memory. Hence we need a frame number to access the page table. Frame number tells the address of a page in main memory.

Now first focus on the VA. It has 32 bits out of which 12 least significant bits are for offset. So Size of page = 4KB.

 

PTE size = 4 Bytes. So one page table contains $2^{10}$ entries.

 

Now look at the VA division. It is divided as 2 | 9 | 9 | 12

So third level page table has the address where the actual frame is loaded. Hence it will require 24 bits.

2nd level PT points to the next level page table. And also one page has $2^{10}$ entries and we are addressing $2^{9}$ entries so one page has 2 page tables. So 1 extra bit is needed to distinguish between the page tables. Hence 25 bits needed. Same for the next level.

 

Here, One page has two page tables. 

Answer:

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