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+78 votes

A processor uses 36 bit physical address and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:

  • Bits 30-31 are used to index into the first level page table.
  • Bits 21-29 are used to index into the 2nd level page table.
  • Bits 12-20 are used to index into the 3rd level page table.
  • Bits 0-11 are used as offset within the page.

The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively

  1. 20,20,20
  2. 24,24,24
  3. 24,24,20
  4. 25,25,24
asked in Operating System by Veteran (59.4k points) | 14.5k views
Since,the virtual address space is 2^32 so, number of pages in the virtual address space should be 2^32/2^12=2^20.... and,so the number of page table entries in the last level should be 2^20 only...
Why are we considering physical address space here??
Because then we would be wasting the remaining physical address space.
what you mean wasting physical memory size?
@Arjun but since the logical address space is 2^32 and physical address space is 2^36.Isn't it implied that the CPU will not be able to address the entire physical memory ?? Please clarify?
Only on a uniprocessor system. For multi processor system, different processes can map to different memory spaces (page tables being different).
@Sir Arjun,Shared Memory in Distributed Environment.Isn't it?All d more architecture varies from processor to processor.:)

Important point --> Page tables need not to be page aligned.

Notice in this question virtual memory is used to create a illusion that  actual physical memory size is less. :)


PS: Although, I should not write thanks message because sometimes it is considered as spamming but I can not control ( Bcz you guys has done really good job) So Thank You @Aruj ji and @Sachin Mittal 1 ji.

This question has maximum views.10k+.:)
Please make a video on this concept so that it will be very helpful because it was mostly confusing to all students .

4 Answers

+102 votes
Best answer

Physical address is $36$ bits. So, number of bits to represent a page frame $ = 36-12 = 24\ bits$ ($12$ offset bits as given in question to address 4 KB assuming byte addressing). So, each entry in a third level page table must have $24$ bits for addressing the page frames. 

A page in logical address space corresponds to a page frame in physical address space. So, in logical address space also we need $12$ bits as offset bits. From the logical address which is of 32 bits, we are now left with $32-12 = 20\ bits$; these $20\ bits$ will be divided into three partitions (as given in the question) so that each partition represents 'which entry' in the $i^{th}$ level page table we are referring to.

  • An entry in level $i$ page table determines 'which page table' at $(i+1)^{th}$ level is being referred. 

Now, there is only 1 first level page table. But there can be many second level and third level page tables and "how many" of these exist depends on the physical memory capacity. (In actual the no. of such page tables depend on the memory usage of a given process, but for addressing we need to consider the worst case scenario). The simple formula for getting the number of page tables possible at a level is to divide the available physical memory size by the size of a given level page table.

$\text{Number of third level page tables possible} = \frac{\text{ Physical memory size}}{\text{ Size of a third level page table}}$
$= \frac{ 2^{36} } {\text{Number of entries in a single third level page table} \times \text{ Size of an entry} }$
$= \frac{2^{36}} {2^9 \times 4} \because \text{ (bits 12-20 gives 9 bits)}$
$= \frac{2^{36}}{2^{11}}$

PS: No. of third level page tables possible means the no. of distinct addresses a page table can have. At any given time, no. of page tables at level $j$ is equal to the no. of entries in the level $j-1$, but here we are considering the possible page table addresses. See Problem 3, second part solution - It clearly says that we should not assume that page tables are page aligned (page table size need not be same as page size unless told so in the question and different level page tables can have different sizes).
So, we need 25 bits in second level page table for addressing the third level page tables.

Similarly we need to find the no. of possible second level page tables and we need to address each of them in first level page table.


$\text{Number of second level page tables possible} = \frac{\text{ Physical memory size}}{\text{ Size of a second level page table}}$
$= \frac{ 2^{36} } {\text{Number of entries in a single second level page table} \times \text{ Size of an entry} }$

$= \frac{2^{36}} {2^9 \times 4} \because \text{ (bits 21-29 gives 9 bits)}$
$= \frac{2^{36}}{2^{11}}$

So, we need 25 bits for addressing the second level page tables as well. 

So, answer is (D). 

There is nothing to edit for such awesome explanation but just adding one of my comment if it is useful - comment. However if anyone finds something to add (or correct) then feel free to do that in my comment.)

answered by Veteran (342k points)
edited by
@saket Who told tht main memory can only be divided equally between pag frames and page tables? Who divides it?

@Joshi As told in the answer, there is no requirement that a given process addresses all available physical memory space. But a physical address must be large enough so that every possible address can be used (by some process).


at third level no. of page table would be...211.

Virtual address space is...2 9 9 12 here...

1st level:- 1 page table, 22 entry and each entry cotains level page table..

2nd level:- 22 page table and each containing containg 29 entry.. .and each entry having next level page table:

3rd level:- 22 * 29 page table and each having third level total no. of entry would be 220.which is equal to the no. of pages in the process(i.e 232-12)...i.e virtual memory devided by page size...



see, Arjun sir's answer..

no. of page tables possible at 3rd level is 225



yes at third level we can have at max 225 tables but out of these how many will be actually used depends on the memory requirements of a process.

@sachine ....i thinnk paging is applied on process so we need to split logical address then why  dividing physical address??

clear the doubt
@Arjun sir,

If at level $i$ we have $2^x$ page tables,then at level $i-1$ we will have $2^x$ entries and each entry will have $x$ bits in its PTE to address next level page table.(Although PTE can have other information also along with $x$ bits)

Please verify

I have a little doubt over calculation as physical address is given in bits (36 bits) and frame size is given in Bytes (4KBytes) . the calculation done is 36-12 = 24 ,so how you took 12 here ? because it should be 215 rather 212 .I'm sorry but I'm not getting this calculation .please clarify ,thank you!

We address a byte and sometimes multiple bytes which is termed a word. There is usually no "bit addressing".
Obviously I'm getting that its byte addressing but my question is specifically about calculations done ,to be more specific I don't get how can bit and byte both involved in single calculation without interchanging one to other .How can byte be subtracted from bits ,wouldn't it lead to wrong calculation ? going at binary level we need bits . few bits becomes bytes and few of those bytes becomes a frame or block or whatever but the ground level is bits only ,isn't ? I see it as you have set of bits for addressing like MM or VM ,in power of 2 for calculative simplicity and then we divide it in index offset etc etc and then address translation through mapping it further where we set few bits (a collection in terms of byte or word) to define frame and it goes like that ,right ? but the binary ground is bit only. I hope you I'm capable of explaining my confusion ..please clarify .thank you!
@Arjun sir

Correct me if I'm wrong, this is what I understood from your solution to this question:

First level page table has 2 bits, so it can point to 4 second level page tables, and each of its entry is of 25 bits.
Second level page tables has 9 bits, so each second level page table can point to 512 third level page tables, and each of its entry is of 25 bits too.
Third level page tables has 9 bits to it, so each third level page table can point to 512 main memory frames, and each of its entry is of 24 bits.
+20 votes

Total no. of physical frames = 2^(36)/2^(12) = 2^24  
Therefore, bits needed to address a physical frame = 24 .
Now, A 3rd level PTE[Page table entry] contains  "bits to address a Physical frame"[final mapping from virtual to physical address] + valid/Invalid bit + some other bits[R/w etc.] .

But, question specifically asks for only "bits needed to address the next level page table or page frame".
So, the bits needed to address the page frame is 24.      

A 2nd level PTE[Page table entry] contains  "bits to address a Physical frame"[Physical address where a 3rd level page resides in main memory ] + valid/Invalid bit + some other bits[R/w etc.] 
So, the bits needed to address the page frame/next page table is 24. 
A 1st level PTE[Page table entry] contains  "bits to address a Physical frame"[Physical address where a 2nd level page resides in main memory ] + valid/Invalid bit + some other bits[R/w etc.] 
The bits needed to address the page frame/next page table is 24. 

Hence , the answer is B .

See figure 2 here for reference  .

answered by Junior (771 points)
You have assumed that page table size is same as a page size.
Page table size is of no use here . A PTE contains the address of the physical frame from where the next level page table starts[The next level page table may span many contiguous frames ; to find the required PTE in this table we use the Bits in the Virtual Address(for that specific level) to index into it ] .

Anyway, In this case every page table comes inside a single physical frame .

Virtual Address is 32 bits.
2[1st level table index]   9[2nd level table index]  9[3rd level table index]  12[offset in the final physical frame]  
So, the 1st level table has 2^2 = 4 PTE   [i.e 4 pointers to 4 different 2nd level tables]
       the 2nd level table has 2^9 = 512 PTE  [i.e 512 pointers to 512 tdifferent 3rd level tables ]
       the 3rd level table has 2^9 = 512 PTE  [i.e 512 pointers to 512  final physical frame ]

Assuming a PTE of maximum 4 Bytes , the maximum space a page table[of any level] can take is 2^11 bytes [less than a frame size].  
Note : N page tables of  2nd (or 3rd) level  will take  N physical frames for each page table respectively.
Exactly, when the page table size is less than the size of a page, we can have more number of page tables than the number of pages possible. i.e., consider page size as the size of the page table and see how many page table entries are required.
this question is asking about  only page frame  bit ,is it ? then why we are calculate all these, it is simply 24 bit,24,24  ..
24 bit for lowest level is fine. But how 24 for other two?
frame no bit remain same for all level page table .because at all level, page table entry is same ...
No. There is no rule like that. You can see the link given in the answer.
sir ,page table entry size is same  for all level . and PTE contain frame bit . so it also remain same.
No. Where you saw this?
from tanenbaum chapter 4 ,structure of page table entry , here also PTE is 4B and it is same for all level of paging then frame bit also same na.. sir am talking about frame bit not page entry address bit

okay. But page frame bit is there only for last level page table as that is the only level referring to a page frame. All previous levels refer to the next level page table. Now, the page table it self can be paged and there are two possibilities

  1. Page table page can be of the same size as page frame
  2. Page table page can be of a different size

Unless specified we can't assume case is 1 though that is common. This question actually is meant to check this concept only. Here, case is 2. 

you are mistaken something  .

page size and frame size must be of same size . Page table entry (aka PTE) minimum must contain frame address (mandatory) plus it sometimes also contains additional data (like flag reference bit ) . so PTE differ .
ohk arjun sir

You can solve these questions- very good ones. 


@Arjunsir by "page table page" you mean page table entry size? i.e. 4 bytes?

"@Arjunsir by "page table page" you mean page table entry size? i.e. 4 bytes?"

No, as i think, the 'page table page' means that during paging the page table itself, the size of page (that will be result of paging page table), and it is different from the actual page size that is given 4KB.
@Rohan7980,Look Page Frame Size is 4 KB n d page table is 4 Bytes.Why to confuse?
+6 votes

Diagram for this ans will be

where 1st level there is 1 page table which contains contains 225 entries

2nd level there are 225 page table and each contains 225 entries

3rd level there are 225 page table and each contains 224 entries

answered by Veteran (84.3k points)
edited by
@srestha,first level page tble contains 2^25 entries cuz there are 2^25 second level page tables??and same for no of entries in each table of second level..and how do you know that there is only 1 table in first level??
and do you mean to say at second level,there re 2^25 tables,each contain 2^25 entries and each entry has 25 bits to address 2^25 entries in a single page table of level 3rd??
@srestha according to ur diagram 1st level page table contains 2^25 entries but according to question it is given that " Bits 30-31 (2 bits) are used to index into the first level page table." i think there will be 2^2 entries in 1st level page table plzz correct if a m wrong....

Actually 2 is no. of page available in 1st level and 225 are number of entries in single page.

@srestha i think  there should be always one page table at 1st level.
  ok but when we r calculating page table size on 1st level like (no of page table entries/index * page table entry size )= 2^2 * 4 B.
  as in sol given by arjun sir when he is calculating 2nd level page size
Number of entries in a single second level page table× Size of an entry= 2^9×4 B
in ur diagram it is given that no of page tables at 2nd level =2^25 at the same time it shows that each page table on 2nd level entries are (0 to 2^25 -1)
nd thnx for quick rply.
0 votes

Here what I want to know is what is the total size required by the page tables?
My explanation: Number of frames : 2^36/2^12=2^24 , now each third level page table can address 2^9 , so total number of third level page tables required to address PA is 2^24/2^9=2^15
Now we have 2^15 entries in the second level page tables , but each second level page table can adres 2^9 pages , so 2^15/2^9 =64 page tables for second level
Now 4 entries per first level PT , and we must address 64 entries for the first level , so 64/4 = 16 first level page tables
Is the above explanation correct?
So : Number of first level PTs=16
Number of scnd level PTs=64
Number of third level PTs=2^15

Am I crct in the abve explanation or is there something wrng?

@Arjun Sir @Praveen Saini Sir plz have a look ! Thank you!

answered by (19 points)
I am doing the same way u mentioned,why is it not correct?

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