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Delayed branching can help in the handling of control hazards

For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false,

  1. The instruction following the conditional branch instruction in memory is executed

  2. The first instruction in the fall through path is executed

  3. The first instruction in the taken path is executed

  4. The branch takes longer to execute than any other instruction

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Answer is A. In order to avoid the pipeline delay due to conditional branch instruction, a suitable instruction is placed below the conditional branch instruction such that the instruction will be executed irrespective of whether branch is taken or not and won't affect the program behaviour.
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reference pattrerson book "the hardware software interface" 3rd edition page no 382 

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Delayed branching is a solution to handle the control hazards. 

Delayed Branching Idea: Just give him something to execute…

Detailed Video Explanation: Delayed Branch Solution for Control Hazards


One way to maximize the use of the pipeline, is to find an instruction that can be safely exeucted whether the branch is taken or not, and execute that instruction. So, when a branch instruction is encountered, the hardware puts the instruction following the branch into the pipe and begins executing it, just as in predict-not-taken. However, unlike in predict-not-taken, we do not need to worry about whether the branch is taken or not, we do not need to clear the pipe because no matter whether the branch is taken or not, we know the instruction is safe to execute. How do we know? The compiler promised it would be safe.

When the program was compiled, the compiler looked at each branch instruction, and tried to find something that could be safely executed, whether we take the branch or not.

https://www.cs.umd.edu/users/meesh/cmsc411/website/projects/branches/delay.html 

Delayed Branching - define the branch such that one (or two) instruction(s) after the branch will always be executed.

Compiler automatically rearranges code to fill the delayed-branch slot(s) with instructions that can always be executed. Instructions in the delayed-branch slot(s) do not need to be flushed after branching. If no instruction can be found to fill the delayed-branch slot(s), the a NOOP instruction is inserted.

https://www.cs.uni.edu/~fienup/cs240f03/lectures/lec21_11-4-03_control_hazards.htm 

Branch delay slots. The ISA is constructed such that one or more instructions sequentially following a conditional branch instruction are executed whether or not the branch is taken. The compiler or assembly language writer must fill these branch delay slots with useful instructions or NOPs (no-operation opcodes). This solution doesn't extend well to deeper pipelines, and becomes architectural baggage that the ISA must carry into future implementations. 

https://people.engr.tamu.edu/djimenez/taco/utsa-www/cs5513-fall07/lecture4.html 

https://www.cs.umd.edu/~meesh/411/CA-online/chapter/handling-control-hazards/index.html 

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