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Below is the screenshot of the question. I found that answer of the Q.10 is 7 and I unable to understand Q.11. Please correct me in Q.10 and Please explain Q.11 meaning and answer.

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This question asks about the unconditional branches. 

To deal with the branches , branch target buffer saves all the target addresses that can occur in a program for both conditional and as well as unconditional branches to save the time required to calculate the target address, otherwise ,it would create many stalls.

The fetch unit also has the ability to recognize branch instructions and to generate the target address. Thus, penalty produced by unconditional branches can be drastically reduced and  the fetch unit computes the target address or refers the branch target buffer and continues to fetch instructions from that address, which are sent to the queue. 
Thus, the rest of the pipeline gets a continuous stream of instructions, without stalling . 

If the instruction is a conditional branch, the resolution of the branch decision occurs in the execution stage of the pipeline ,
which will create many stalls. If it is specified particularly that a particular stage computes target address, then from the next cycle we will fetch the target instruction , but if there is no information like this , we will consider that branch instruction completes execution, only then target instruction will be loaded.

For 1st part , as it is a unconditional branch, the pipeline gets a continuous stream of instructions, without stalling 
so S1 occurs total 6 times , the answer will be D). 

For 2nd part, the answer will be D). 

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  1 2 3 4 5 6 7 8 9 10 11 12
I1 S1 S2 S3 S4                
I2   S1 S2 S3 S4              
I3     S1 S2 S3 S4            
I8       S1 S2 S3 S4          
I9         S1 S2 S3 S4        
I10           S1 S2 S3 S4      
                         
                         
                         
                         
                         
                         

USing branch target ..buffer.. that stores the branch targets of earlier computed..branches...which can computed..once..and can be reffered..any no. of time...so after I3 ..I8 will directly..executed....

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IT IS A HYPOTHETICAL PIPELINE

GIVEN IN QUESTION 

ALL INSTRUCTION ARE PROCEED THROUGH ALL THE STAGES

SO execution cycle is

S4       I1 I2 I3 I4 I5 I6 I8 I9 I10
S3     I1 I2 I3 I4 I5 I6 I8 I9 I10  
S2   I1 I2 I3 I4 I5 I6 I8 I9 I10    
S1 I1 I2 I3 I4 I5 I6 I8 I9 I10      


when target address is achieved from I3 at S4, up to I6 instruction is already decoded and then start from I8

SO decoded instruction is  I1 I2 I3 I4 I5 I6 I8 I9 I10

ANS  (b)

IN PART TWO

ANS (a) 

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