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Analyse the circuit in Fig below and complete the following table

a b $Q_n$
0 0  
0 1  
1 0  
1 1  

asked in Digital Logic by Veteran (59.5k points)
edited by | 811 views
0
@Arjun Sir here question is incomplete
0
why?
0
where is c) question?
0
yes.. Actually that was moved to a new question- answer is yet to be moved. Each linked question was made separate so as to be included in exam when created.
0

1 Answer

+13 votes
Best answer

(a) The output of the circuit given as :

$Q=aQ_{n-1}+ab+bQ_{n-1}$

Hence,  

$Q_{n}=Q_{n-1}(a+b)+ab$

$00 \implies  Q_{n-1}(0+0) + 0.0 = Q_{n-1}(0) + 0 = 0+0 = 0$

$01 \implies  Q_{n-1}(0+1) + 0.1= Q_{n-1} (1)+ 0 = Q_{n-1}+0 =  Q_{n-1}$

$10 \implies  Q_{n-1}(1+0) + 1.0 = Q_{n-1} (1) + 0 = Q_{n-1}+0= Q_{n-1}$

$11 \implies Q_{n-1}(1+1)+ 1.1 =Q_{n-1}(1) + 1 =Q_{n-1}+1 = 1$

a b Qn
$0$ $0$ $0$
$0$ $1$ $Q_{n-1}$
$1$ $0$ $Q_{n-1}$
$1$ $1$ $1$

(c)

All the flip flops are operated by same clock, together all takes one propagation delay .

All the AND gates consumes one propagation delay individually.

Total propagation delay $= T_{\text{CLK}} \geq T_{\text{flip-flop}} +T_{\text{ AND gates}}$

$\qquad \qquad = 10ns+(10+10+10)ns = 40ns$

Maximum clock frequency $=1/T_{\text{CLK}} = 1/40 ns= 10^{9}/40 = 25 \text{ MHz}$

So, maximum clock frequency at which the counter can operate is $25 \text{ MHz}.$

answered by Active (3.3k points)
edited by
+1
How the propagation delay is calculated..??

Here delay should be due to one OR gate and one AND gate.
0

@vaishali Part c is different. See this

https://gateoverflow.in/26442/gate1991_5-c

0

11 =>  Qn-1(1+1) + 1.1 = Qn-1 (1) + 1 = Qn-1+1 = 1 hwo it is equals to 1

0
1+x=1 here x=Q n-1 .


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