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+12 votes
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Analyse the circuit in Fig below and complete the following table

a b $Q_n$
0 0  
0 1  
1 0  
1 1  

 

asked in Digital Logic by Veteran (59.4k points)
edited by | 688 views
0
@Arjun Sir here question is incomplete
0
why?
0
where is c) question?
0
yes.. Actually that was moved to a new question- answer is yet to be moved. Each linked question was made separate so as to be included in exam when created.
0

1 Answer

+13 votes
Best answer

(a)  The output of the circuit given as :-

Qn=aQn-1+ab+bQn-1

Hence,  

Qn=Qn-1(a+b)+ab

00 =>  Qn-1(0+0) + 0.0 = Qn-1 (0) + 0 = 0+0     = 0

01 =>  Qn-1(0+1) + 0.1 = Qn-1 (1) + 0 = Qn-1+0 =  Qn-1

10 =>  Qn-1(1+0) + 1.0 = Qn-1 (1) + 0 = Qn-1+0 =  Qn-1

11 =>  Qn-1(1+1) + 1.1 = Qn-1 (1) + 1 = Qn-1+1 = 1

a b Qn
0 0 0
0 1 Qn-1
1 0 Qn-1
1 1 1

 

(c)

All the flip flops are operated by same clock , together all takes one propagation delay .

All the AND gates consumes one propagation delay individually.

Total propagation delay = TCLK >= T flip-flop +T AND gates

                                            = 10ns+(10+10+10)ns = 40ns

Maximum clock frequency =1/TCLK = 1/40ns= 109/40 = 25 MHz

So,Maximum clock frequency at which the counter can operate is 25 MHz

answered by Active (3.3k points)
selected by
+1
How the propagation delay is calculated..??

Here delay should be due to one OR gate and one AND gate.
0

@vaishali Part c is different. See this

https://gateoverflow.in/26442/gate1991_5-c

0

11 =>  Qn-1(1+1) + 1.1 = Qn-1 (1) + 1 = Qn-1+1 = 1 hwo it is equals to 1



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