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  1. Using D flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines:
    1. Clock $\text{CLK}$

    2. Three parallel data inputs $A, B, C$

    3. Serial input $S$

    4. Control input $\text{load} / \overline{\text{SHIFT}}$.

asked in Digital Logic by Veteran (59.6k points) | 284 views

1 Answer

–2 votes
ii. three parallel inputs A,B,C
answered by (457 points)
0
@Khamer can you please explane how?


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