1. CYCLE STEALING MODE
Once the DMA controller is granted access to the system bus by the CPU,it transfer the one byte of data then it releases the memory access to cpu . again for another byte of transfer it has to acquire bus access by cpu via BR and BG signal(BUS REQUEST and BUS GRANT).For Every Byte of Transfer it acquires bus access and releases it until entire Block of Data Transferred.
So , here transfer time to send 1 byte of data = 1byte/50kbps= 20 μsec
now, total time to transfer one byte data= time to transfer bus control at the beginning + bus cycle time to transfer one byte data + transfer time of device to send one byte data+ release bus control =( .3 +.7+20+.3)=21.3 μsec
now to transfer total block of 100 byte data = 21.3 *100=2130 μsec time required . so none option correct here
2. BURST MODE
Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU. CPU is disabled to use Memory Bus for long time.it will not release bus access until entire Block of Data Transferred.
so here transfer time = 100 byte/ 50 kbps= 2 msec
added to this is the time to transfer bus control at the beginning and end of transfer which is 300+300= 600 nsec which is negligible. option b is correct
link : https://en.wikipedia.org/wiki/Direct_memory_access