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Consider the following loop.

𝑙𝑜𝑜𝑝:
1. 𝑆𝑈𝐵𝐼 𝑅1,𝑅1,#1

2. 𝐿𝐷 𝑅3,0(𝑅2)

3. 𝐿𝐷 𝑅4,4(𝑅2)

4. 𝑀𝑈𝐿 𝑅5,𝑅3,𝑅4

5. 𝐴𝐷𝐷 𝑅3,𝑅5,𝑅6

6. 𝐴𝐷𝐷𝐼 𝑅2,𝑅2,#8

7. 𝐵𝑁𝐸𝑍 𝑅1,𝑙𝑜𝑜𝑝

8. 𝐴𝐷𝐷 𝑅10,𝑅11,𝑅12

identify all data dependencies (potential data hazards) in the given code snippet. Assume the loop takes exactly one iteration to complete. Specify if the data dependence is RAW, WAW or WAR.

solution:   1) 1  7 (RAW)
2) 2  4 (RAW)
3) 2  5 (WAW)
4) 2  6 (WAR)
5) 3  4 (RAW)

6) 3  6 (WAR)

7) 4  5 (RAW)
8) 4  5 (WAR)

There is no WAR or RAW from 7  1 because the loop only executes for a single iteration.please explain how 

in CO and Architecture by | 330 views
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how WAR possible , register write is much after the read in five stage pipeline
0
At 7 their is condition so before looping or not looping we need to check the condition BNEZ (branch if not equal zero ) so we need to check value in R1 without reading we cannot checkit so their is RAW as R1 is written in line 1
0
okk thanks i got first but i read WAR is not possible in 5 stage pipeline so please explain about WAR in this example
0

WAR is  for 2-6 ,3-6 ,4-5 na

At 2-6 : 2 ------  R2 is read and stored in R3 

           6------ R2 is initially read and written  so we get (WAR)

At 3-6 : 3 -----R2 is read and stored in R4

            6------ R2 is initially read and written  so we get (WAR)

At 4-5 : 4 ------- R3 is read here

            5 ------ R3 is written so (WAR)

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