A NAND gate produces output 1 when one of its input is a 0. So, for $F$ to be one, one of its input should be 0, which inturn means all the inputs of any one of the first level NAND gates be 1's.
When $B=C=D=1$, the second NAND gate gives output $1\;($since one input $\bar B$ is $0)$ and hence won't affect the final output $F$ if $A$ changes.
If $A=1$, the third NAND gate gives output $0$ and $F = 1$.
If $A = 0$, first NAND gate gives output $1$ and final output is $F=1$. But if the propagation delay of the first gate is more- considering an extra NOT gate for $\bar A$, output could have been $F=0$ for a moment- static 1 hazard and this happened when A changed from 1 to 0. A similar hazard can happen when A changes from 0 to 1, but only if the third gate is having higher propagation delay compared to first.