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+7 votes

Consider the logic circuit given below.

The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?

- 5
- 11
- 16
- 27

+22 votes

Best answer

I think the answer is A. 5.

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns.

Correct me if I am wrong.

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns.

Correct me if I am wrong.

+3 votes

If we ignore delay of exor gate then total delay is 16 . NOT and OR gate running independently but AND gate can't run until NOT gate give output to AND gate.So NOT and AND are working sequencially . so (6+10) total delay.

+2 votes

'**inverter**' and '**or**' gate starts at the same time while '**and**' gate waits for '**inverter**' output.

# - '**inverter**' and '**and**' gate are serially connected so time required is 6+10=**16ns**.

$ -'**or**' gate requires **11ns**.

**#** and **$** is parallely connected so total time required is max(#,$) =max(16,11) =**16ns**.

Total time required is **16ns**.

(i am not sure...its my answer)

–2 votes

**Ans D)**

The gate is at stable state when all gates are active . Every gates are at different levels.All gates will be active after 6+10+11=27 ns.

(XOR gate activation time is not given . So, we assume it as negligible )

+1

@srestha .... I think net delay of inverter and and gate = 6 + 10 ( because both are in series ) which is parallel to or gate delay = 11ns ... so delay before xor should be 16ns ...right ??

Now we have one more XOR gater but xor delay is not given in the question but xor can be designed by the help of inverter , AND gate and OR gate ... so how can we neglect xor gate delay ??

Now if we calculate xor gate delay then I think min would be 6 + 10 +11 ( A'B + AB') = 27ns ...

So ans should be 16 ns + 27ns = 43ns

please clear my doubt ...

Now we have one more XOR gater but xor delay is not given in the question but xor can be designed by the help of inverter , AND gate and OR gate ... so how can we neglect xor gate delay ??

Now if we calculate xor gate delay then I think min would be 6 + 10 +11 ( A'B + AB') = 27ns ...

So ans should be 16 ns + 27ns = 43ns

please clear my doubt ...

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