Consider the logic circuit given below.
The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?
'inverter' and 'or' gate starts at the same time while 'and' gate waits for 'inverter' output.
# - 'inverter' and 'and' gate are serially connected so time required is 6+10=16ns.
$ -'or' gate requires 11ns.
# and $ is parallely connected so total time required is max(#,$) =max(16,11) =16ns.
Total time required is 16ns.
(i am not sure...its my answer)
Please provide correct answer with relevant expalnation
The gate is at stable state when all gates are active . Every gates are at different levels.All gates will be active after 6+10+11=27 ns.
(XOR gate activation time is not given . So, we assume it as negligible )