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Consider the logic circuit given below.

The inverter, AND and OR gates have delays of 6, 10 and 11 nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for Q before it becomes stable?

1. 5
2. 11
3. 16
4. 27
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CAN any1 provide vedio solutio for this question???? and also can any1 provide me link of youtube so that i can understand these kinds of problems??
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I think the answer is A. 5.

Because the inverter and the AND gate will take total of 6 + 10 = 16 ns. And the OR gate will take 11 ns. As 11 < 16, the output of OR gate will immediately comes at XOR. 16 - 11 = 5 ns more will be required the get the actual output. So the duration of glitch is 5 ns.

Correct me if I am wrong.
by (175 points)
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I guess you logic is correct..
If we ignore delay of exor gate then total delay is 16 . NOT and OR gate running independently but AND gate can't run until  NOT gate give output to AND gate.So NOT and AND are working sequencially . so (6+10) total delay.
by Active (3.1k points)

'inverter' and 'or' gate starts at the same time while 'and' gate waits for 'inverter' output.

# - 'inverter' and 'and' gate are serially connected so time required is 6+10=16ns.

$-'or' gate requires 11ns. # and$ is parallely connected so total time required is max(#,\$) =max(16,11) =16ns.

Total time required is 16ns.

(i am not sure...its my answer)

by (53 points)
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I also think it should be 16ns as stated by Kiran123.
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Please check my answer. The question asks for the time duration of glitch before Q becomes stable. The 16 ns is the time taken to reflect the final output. But before that output, due to the time difference of gates we will get some glitch at XOR. I hope this helps.
option- (C)
by Boss (15.6k points)

Ans D)

The gate is at stable state when all gates are active . Every gates are at different levels.All gates will be active after 6+10+11=27 ns.

(XOR gate activation time is not given . So, we assume it as negligible )

by Veteran (117k points)
+1
@srestha .... I think net delay of inverter and and gate = 6 + 10 ( because both are in series ) which is parallel to or gate delay = 11ns ... so delay before xor should be 16ns ...right ??

Now we have one more XOR gater but xor delay is not given in the question but xor can be designed by the help of inverter , AND gate and OR gate ... so how can we neglect xor gate delay  ??

Now if we calculate xor gate delay then I think min would be  6 + 10 +11  ( A'B + AB') = 27ns ...

So ans should be 16 ns + 27ns = 43ns

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yes I also have this doubt
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some say 16 some one say 5 what is correct Answer pls replay
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I think 16 is right because...by stability it means by what time both the inputs to the glitch are available , because nothing is specified for XOR gate , thus we cant assume about time constraints upon glitch .