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Consider the logic circuit given below.

The inverter, AND and OR gates have delays of $6, 10$ and $11$ nanoseconds respectively. Assuming that wire delays are negligible, what is the duration of glitch for $\text{Q}$ before it becomes stable?

  1. $5$
  2. $11$
  3. $16$
  4. $27$
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Ans D)

The gate is at stable state when all gates are active . Every gates are at different levels.All gates will be active after 6+10+11=27 ns.

(XOR gate activation time is not given . So, we assume it as negligible )

Answer:

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