ISRO2016-19

Question

Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to $2$ gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is

• A. $3.2$
• B. $3.0$
• C. $2.2$
• D. $2.0$

Comments

https://gateoverflow.in/8288/gate2015-1_38

Answer 1

$\underline{\textbf{Answer:}\Rightarrow}\;\mathbf{A})\;3.2$

$\underline{\textbf{Explanation:}\Rightarrow}$

$\color{blue}{\underline{\textbf{For Non-Pipelined System:}\Rightarrow}}$

Given frequency $\mathbf{ = 2.5 GHz}$

$\therefore 1\; \text{Cycle time} = \mathbf{\dfrac{1}{2.5Gs} }= \dfrac{1}{2.5}\;\text{nano seconds}$

$\therefore \text{Total Time}  = 4\times \frac{1}{2.5} \text{nano seconds} =\dfrac{4}{2.5}\;\text{nano seconds}$

$\color{blue}{\underline{\textbf{For Pipelined System:}\Rightarrow}}$

 $\textbf{Average CPI} = 1\;\;[\because \text{It is given that pipeline has no stalls.}]$

This also proves the fact that pipeline is also $\color{magenta}{\text{independent of the number of phases}}$, [so there would be $\color{red}{\text{no change}}$ if the question was asked for $\mathbf 6$ stages also.]

Similarly, as above:

$\mathbf{Frequency = 2\;GHz}$

$\therefore\;1\text{ cycle time} =\dfrac{1}{2} \;\text{nano seconds}$

$\therefore \textbf{Speed-up} = \dfrac{\text{Time without pipelining}}{\text{Time with pipelining}} = \dfrac{\dfrac{4}{2.5}}{\dfrac{1}{2}} = 3.2$

$\therefore\;\mathbf{3.2}$ is the correct answer.

Answer 2

Option A

 

let p1 be non pipelined processor

k=4    f1=2.5GHz

 

let p2 be pipelined processor

k=5   f2=2GHz

 

Speedup=  k*(1/f1)  /  (1/f2)

= 8/2.5

=3.2