where is the ckt?

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+2 votes

assuming f as Y in order to y=1 (steady) state the last AND gate must have both input as 1

so C=1 (so choice C is out) and for other input to be 1 either B=0 (which ensures output of 2nd NAND gate as 1)

or A=1 as it ensure the output of second NAND gate as 0 if other input is also 1 , now which is f which may be 0 or 1 so to be safe side leave this

i.e B=0 and A=1 or 0 C=1 choice A)satisfy and also choice D)

hence ans should be A and also D

so C=1 (so choice C is out) and for other input to be 1 either B=0 (which ensures output of 2nd NAND gate as 1)

or A=1 as it ensure the output of second NAND gate as 0 if other input is also 1 , now which is f which may be 0 or 1 so to be safe side leave this

i.e B=0 and A=1 or 0 C=1 choice A)satisfy and also choice D)

hence ans should be A and also D

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