6 votes 6 votes In a positive edge triggered $J$-$K$ flip flop , if $J$ and $K$ both are high then the output will be ______on the rising edge of the clock : No change Set Reset Toggle Digital Logic ugcnetcse-june2016-paper2 digital-logic flip-flop + – Sanjay Sharma asked Jul 10, 2016 • edited Jun 7, 2020 by Sabiha banu Sanjay Sharma 4.1k views answer comment Share Follow See all 0 reply Please log in or register to add a comment.
Best answer 4 votes 4 votes Ans 4) Toggle When J = 1 and K = 1 , The output continuously Toggles from 1 to 0 and 0 to 1. At the end Output is indeterminate. This condition is called as Race around Condition. This happens when Propagation Delay is less than the Pulse width. Refer : http://ecetutorials.com/digital-electronics/jk-flip-flop/ for more on J K Flip Flop Jithin Jayan answered Jul 10, 2016 • selected Jul 16, 2016 by Sanjay Sharma Jithin Jayan comment Share Follow See all 0 reply Please log in or register to add a comment.