Status register(SR):
→ A status register is a collection of status flag bits for a processor.
→ The status register is a hardware register that contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor.
→ The status register lets an instruction take action contingent on the outcome of a previous instruction.
Interrupt service register(ISR):
→ Interrupt service routine(ISR) is a special block of code associated with a specific interrupt condition.
→ Interrupt handlers are initiated by hardware interrupts, software interrupt instructions, or software exceptions, and are used for implementing device drivers or transitions between protected modes of operation, such as system calls.
Interrupt mask register(IMR):
→ The Interrupt Mask Register is a read and write register.
→ This register enables or masks interrupts from being triggered on the external pins of the Cache Controller.
→ The IMR is used to disable (Mask) or enable (Unmask) individual interrupt request inputs. This is also an 8-bit register.
Interrupt request register(IRR):
→ It stores all the interrupt inputs that are requesting service.
→ It is an 8-bit register, one bit for each interrupt request.
→ It keeps track of which interrupt inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on it, then the corresponding bit in the IRR will be set.
→ The content of this register can be read to know the status of pending interrupts.
