7 votes 7 votes closed with the note: https://gateoverflow.in/78338/dma-cycle-stealing#a78430 -> Same concept Solution : Some one please explain with correct sequence of steps in each mode and a rough timing diagram. CO and Architecture co-and-architecture dma + – dd asked Jul 13, 2016 • retagged Nov 13, 2017 by Arjun dd 2.0k views comment Share Follow See all 14 Comments See all 14 14 Comments reply Show 11 previous comments Kaluti commented Oct 20, 2017 i edited by Kaluti Dec 23, 2018 reply Follow Share It is the property of cycle stealing mode where only 1 byte is transferred not the entire the data that too at bus speed and when we are sending the entire data it should be at io device transfer rate not at system bus speed in burst mode. system bus only matters at bus speed 1 votes 1 votes prayas commented Nov 10, 2017 reply Follow Share How can you neglect the time taken by the device to buffer 1 byte of data?It is 10 microsecond which isn't negligible even if we pipeline it? 0 votes 0 votes Kaluti commented Dec 23, 2018 reply Follow Share In burst mode CPU will not be blocked full time I think 0 votes 0 votes Please log in or register to add a comment.