William Stalling Computer Organization I/O (DMA) question CYCLE stealing VS Burst Mode closed

Question

Solution : 

Some one please explain with correct sequence of steps in each mode and a rough timing diagram.

Comments

For cycle stealing, we have to add 2.56 ms and 128us.

Here , answer is showing only extra overhead in cycle stealing.

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Since only tie up is asked, cycle stealing solution is correct. But burst mode is confusing because after getting the control of bus then after that also some time must be required for sending data to memory.

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Ya for every byte transfer time of io device should also be included here

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The question is asking

....for how much time the bus is tied up?

So, both answers are correct

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please give a detail answer. Thanks !

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In burst mode, the sequence of transferring the data is as follows:

1. Gain the control of the bus ( by sending BUS GRANT request to CPU and subsequently CPU acknowledges the same)

2. Transfer the entire data in single bus cycle. The CPU floats the data bus during this entire transfer.

3. DMA gives back the control to CPU.
 

In cycle stealing mode following things happen for each byte of data to be transferred:

1.  Gain the control of the bus

2. Transfer the byte of data. The bus is flaoted during the transfer.

3. DMA gives back the control of the bus to CPU

Debashish, I previously thought that the answer is correct but now 1 more doubt triggered.

See the timing diagram of DMA at http://www.uotechnology.edu.iq/dep-laserandoptoelec-eng/branch/lectures/microprocessor/24.pdf

The bus isnt available only for a single cycle (and hence the name cycle stealing). So, we shouldnt be considering the time when the bus is being transfeered to DMA/CPU, right? We should only consider the time when the data is being transfrred, right?

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https://gateoverflow.in/62528/cycle-stealing-dma

One more reference for when the buses would be floated.

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@Debashish. I will try to explain the entire process for cycle stealing and burst mode of transfer in DMA.

The concept of cycle stealing is like this:

1. Buffer the byte into the buffer

2. Inform the CPU that the device has 1 byte to transfer (i.e bus grant request)

3. Transfer the byte ( at system bus speed)

4. Release the control of the bus back to CPU.

Before moving on transfer next byte of data, device performs step 1 again so that bus isnt tied up and the transfer wont depend upon the transfer rate of device.

So, summary is, for 1 byte of transfer of data, time taken

= time required for bus grant + 1 bus cycle to transfer data + time required to release the bus

The concept of burst mode in DMA is like this:

1. Bus grant request time

2. TRansfer the entire block of data at transfer rate of device because the device is usually slow than the speed at which the data can be transferred to CPU

http://www.krchowdhary.com/co/ttut5-sol.pdf

http://www.plantation-productions.com/Webster/www.artofasm.com/Windows/HTML/IOa2.html

3. Release the control of the bus back to CPU

So, total time taken to transfer the specified number of bytes

= Bus grant request time + (#bytes to be transferred) * (memory transfer rate) + Bus release control time

Now, the reason why I think the bus is tied up during the bus grant request and bus release is bcause of the control actions that take place before the transfer and after the transfer. Refer slide 2.

http://nptel.ac.in/courses/106103068/module06_io/lect_04_dma/slides/slide2.htm

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Lets look at the answers:

1. Burst mode

TOtal time for which bus is tied up

= time for bus grant request

   + (#bytes to be transfrred) * ( device transfer rate)

   + time for bus release

= 250ns + 2.56ms +250ms

= 2.56 ms approx

2. Cycle stealing mode

time for which the bus is tied up during 1 byte transfer

= time for bus grant request

   + time to transfer the data to memory at system bus rate( i.e. 1 cycle)

   + time for bus release

= 250ns + 500ns +250ns

= 1000ns

Thus, time for which the bus is tied up to transfer 128 bytes = 128 * 1000ns = 128 microsec

I hope you got it :)

   

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Very nice explanation Sushant.I need to clarify one think.In the burst mode. At 2.56 that device has just finished preparing last byte ,so it will take one memory cycle extra to transfer that byte?

Because at 2.56 is the time by which last bit of the data is accessed and now this needs to be transferred to CPU?

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@rahul Sharma.

Just ignore that.Byte preparation and byte transfer just take place parallel....its just pipelining.

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@ Sushant Gokhale sir, IF in cycle stealing mode we  prepare $1B$ and can send it with the speed of BUS then why cant' we ready entire data and  send it with the speed of BUS.

Moreover, If we transfer data with the speed of Disk in Burst mode then our CPU will be blocked for 100% of the time which is not the case.

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It is the property of cycle stealing mode where only 1 byte is transferred  not the entire the data that too at bus speed

and when we are sending the entire data it should be at io device transfer rate  not at system bus speed in burst mode.  system bus only matters at bus speed

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How can you neglect the time taken by the device to buffer 1 byte of data?It is 10 microsecond which isn't negligible even if we pipeline it?

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In burst mode CPU will not be blocked full time I think