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Consider addition in two's complement arithmetic. A carry from the most significant bit does not always correspond to an overflow. Explain what is the condition for overflow in two's complement arithmetic.
asked in Digital Logic by Veteran (68.8k points) | 347 views
if the sign bit of both the signed numbers is not same as the sign bit of the product, then there is an overflow.

2 Answers

+8 votes
Best answer
XOR of $C_{in}$ with $C_{out}$ of the msb position.
answered by Veteran (30.5k points)
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+5 votes

(a) In 2's complement addition Overflow happens only when :

  • Sign bit of two input numbers is 0, and the result has sign bit 1.
  • Sign bit of two input numbers is 1, and the result has sign bit 0.
answered by Veteran (35.9k points)

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