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Consider a system with a virtual address size of 64MB (2^26), a physical memory of size 2GB (2^31), and a page size of 1K (2^10). Under the target workload, 32 processes (2^5) are running; half of the processes are smaller than 8K (2^13) and half use the full 64MB virtual address space. Each page has 4 control bits.

Answer these 

What is the size of a single top-level page table entry (and why)? 

What is the size of a single bottom-level page table entry (and why)? 

Compute the total space overhead for the entire system. 

in CO and Architecture by Boss (45.4k points)
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no. of frames =      231/210 = 221

assume memory byte addressable..

  bottom level page table entry must contain 21 bits to address frames + 4 control bits = 25 but memory is byte addressable it means we can have entry in multiple of 8bits ...so must be 32 instead of 25..

bottom level pg table entry size = 32 bits

by Boss (10.1k points)
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what is that top and bottom level page table entries ?
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