Dma bus time

Kriss Singh asked Sep 13, 2014 • retagged Nov 13, 2017 by Arjun

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Cycle steal mode

CO and Architecture
dma
co-and-architecture
normal

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Kriss Singh asked Sep 13, 2014 • retagged Nov 13, 2017 by Arjun

Kriss Singh

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spriti1991

commented Mar 29, 2015

complete the question please !

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adeemajain answered Jan 13, 2019

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iarnav asked Oct 5, 2018

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#CO DMA modes and % of time CPU stays idle.
Consider y μs is cycle time / transfer time (for memory) x μs is data transfer time / preparation time (for disk) then % of time CPU idle in CYCLE STEALING MODE is = y/x and % of time CPU idle in Burst MODE is = (y)/(x+y) May someone please explain how is this Cpu idle time is calculated in both cycle stealing time and burst mode

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ankitgupta.1729 asked Jul 29, 2017

8,234 views

% time of CPU blocked in DMA
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ankitgupta.1729 asked Jul 29, 2017

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2 answers

Sanket_ asked Dec 6, 2016

636 views

CPU blocked time in DMA
Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing mode where by whenever 1 B word is ready it is sent to memory, ... . The time for each memory cycle is 50 nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is ______

Consider a disk drive with 16 surfaces, 512 tracks / surface, 256 sectors / track, 8 KB / sector with a rotation speed of 3600 rpm. The disk is operated in cycle stealing...

Sanket_

636 views

Sanket_ asked Dec 6, 2016

CO and Architecture
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