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In Cycle Stealing, does the DMA interrupt the processor everytime, or it uses the cycle while the processor remains unknown of the fact?
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In DMA's cycle stealing mode of operation, the DMA controller puts the CPU on hold for each byte of data to be transferred. The processor thus knows the fact that DMA controller is using the bus. A more detailed description is given below:

  1. Each time a peripheral wants to transfer a byte of data, it asserts the DMA request line to the DMA controller.
  2. The DMA controller interrupts the CPU by enabling the CPU HOLD request pin.
  3. The CPU temporarily suspends the current execution and sends the HOLD  ACK (HOLDA) signal back to to the DMA controller. The CPU also floats the address, data and control buses.
  4. The DMA controller in turn, acknowledges the peripheral by asserting the DMA Acknowledge line. It then places the memory address to the address bus.
  5. The peripheral responds to the DMA ACK by putting its data byte to the data bus.
  6. Memory responds to the MEMR or MEMW signal accordingly by transferring the byte.
  7. At the end of the cycle, the DMA controller disables the CPU HOLD signal. The CPU can now resume its execution until the next DMA request arrives.

This is repeated for every byte of data to be trnasferred. In contrast, a DMA's burst mode operates differently. The entire block of data is transferred before the DMA controller can return control back to CPU.

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I think the CPU cycle which does not use memory...DMA can steal those ones. But cpu should know about that.
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Q1.  Does the DMA interrupt the processor everytime?

Yes DMA do interrupt the processor each time it has do data transfer. Frequency of interruption depends on the no of subsequent requests  for IO and the mode of DMA operation.

DMA operation modes: 

  •  cycle stealing : in this mode DMA interrupt the processor each time it has a byte data to transfer. This last as per the data count value. So frequent interruption needed to service one IO request.
  • burst mode : in this mode, DMA interrupt the processor only one time (per request from the IO )  and does the bulk data transfer.

Q 2 . it uses the cycle while the processor remains unknown of the fact?

Yes DMA uses the processor cycle if processor needs to use the BUS while the BUS is temporarily owned by DMA. 

Following extract explains the state of processor while DMA is in action 

                                - from Computer Organization and Architecture: William Stallings

so as per the above paragraph, processor is not suspended until it need to use the BUS.

In a situation where processor need the BUS and it find that DMA is the BUS master , it just wait till it get the bus ownership  i.e. remain idle. <---  we can say here that DMA stole a  cycle 

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This is from Computer Organization and Architecture by William Stallings:

The DMA module uses the system bus only when the processor does not need it, or it must force the processor to suspend operation temporarily. The latter technique is more common and is referred to as cycle stealing, because the DMA module in effect steals a bus cycle.

So it sounds implementation specific (as always is the case with most technical facts in bigger systems) and in most implementations DMA must force the processor to suspend operation and free up the system bus.

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