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Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that

  1. T1 ≤ T2
  2. T1 ≥ T2
  3. T1 < T2
  4. T1 and T2 plus the time taken for one instruction fetch cycle
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2 Comments

The Archive page of the link mentioned as a reference by Arjun Sir (Original page is deleted now)

http://web.archive.org/web/20160324083651/http://www.cs.wvu.edu/~jdm/classes/cs455/notes/tech/instrpipe.html

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PIPELINING SYSTEM:
Pipelining is an implementation technique where multiple instructions are overlapped in execution. It has a high throughput (amount of instructions executed per unit time). In pipelining, many instructions are executed at the same time and execution is completed in fewer cycles. The pipeline is filled by the CPU scheduler from a pool of work which is waiting to occur. Each execution unit has a pipeline associated with it, so as to have work pre-planned. The efficiency of pipelining system depends upon the effectiveness of CPU scheduler.
NON- PIPELINING SYSTEM:
All the actions (fetching, decoding, execution of instructions and writing the results into the memory) are grouped into a single step. It has a low throughput. Only one instruction is executed per unit time and execution process requires more number of cycles. The CPU scheduler in the case of non-pipelining system merely chooses from the pool of waiting work when an execution unit gives a signal that it is free. It is not dependent on CPU scheduler.
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4 Answers

55 votes
 
Best answer

Here we are comparing the execution time of only a single instruction. Pipelining in no way improves the execution time of a single instruction (the time from its start to end). It increases the overall performance by splitting the execution to multiple pipeline stages so that the following instructions can use the finished stages of the previous instructions. But in doing so pipelining causes some problems also as given in the below link, which might slow some instructions. So, (B) is the answer. 

http://www.cs.wvu.edu/~jdm/classes/cs455/notes/tech/instrpipe.html

edited by
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18 Comments

Thanks !!!
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What is the case for $T_1 = T_2$? (as it is implied by $T_1 \le T_2$)
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when buffer delays are negligible in pipeline $T_1 = T_2$
39
@Arjun Sir, the link is not accesible. Error 404 : Not Found. Please check.
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Thanks dude
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@rishi

Try this http://archive.is/XPYL (Its saved page of that link)

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thanks @smsubham
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@thor T1=T2 when buffer delay is negligible as well as each stage delay are equal
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@Arjun sir, in "Pipelining in no way increases the execution time of a single instruction" wouldn't "improves" instead of "increases" be more appropriate? Because pipelining does increase the execution time of a single instruction sometimes.
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Thanks .You're correct .
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 Sir If T1>t2 is one of the options along with T1>=T2 then which option to choose?

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@Arjun sir can you update the link, its giving 404 Error
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@Arjun sir Link is not working kindly update it.

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@Rishi yadav Yes got it thank you

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@Arjun Sir
Given link is not working
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20 votes

When pipeline stages are perfectly balanced (uniform delay) then 1 task execution time in the pipeline is also equal to one task execution time in the non-pipeline.

$Ex: k(stages)=4, n(instruction)=1,cycle time=2ns$

Execution time of pipeline $= 8ns$

Execution time of non-pipeline $= S1+S2+S3+S4=2+2+2+2=8ns$


When pipeline stages are not perfectly balanced then 1 task execution time in the pipeline is greater than one task execution time in the non-pipeline.

Note: If execution time is greater than why we are using pipelining ? It is greater only for one task but when $n\rightarrow\infty$ pipeline performance is way better than non-pipeline.

$Ex: k(stages)=4, n(instruction)=1,cycle time=max(2,6,4,2)=6$

Execution time of pipeline $= 24ns$

Execution time of non-pipeline $= S1+S2+S3+S4=2+6+4+2=14ns$


$\therefore T1\geqslant T2$

1 vote
T1>=T2 because in order the carry out the pipelining we need to add certain buffers between different stages of a pipeline in order to control the flow of data and maintaining CPI for intructions.
–4 votes
Everywhere answer given is (B) I cant understand why ... can anyone explain?

I am getting (A)

3 Comments

Suppose

- each stage takes "T" unit of time both in pipelined and non-pipelined setup.

- Total Pipeline Stages = K = Total number of stages in non-pipelined

- Number of Instructions = N = 1 in this case

Pipelined:

TotalTime T1 = [K + (N-1)] * T = KT

Non-Pipelined:

TotalTime T2 = KNT = KT

Moreover there are intermediate buffers in between stages of pipelined processors which might consume some time. Therefore  T1 >= T2
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@sameer2009 What is the K denote in Non-pipeline ?
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Actually, K is number of stages via which an instruction will go through. Here K is independent whether processor is pipelined or non-pipelined.
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Answer:

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