The Gateway to Computer Science Excellence
First time here? Checkout the FAQ!
+23 votes

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that

  1. T1 ≤ T2
  2. T1 ≥ T2
  3. T1 < T2
  4. T1 and T2 plus the time taken for one instruction fetch cycle
asked in CO and Architecture by Veteran (52.1k points)
retagged by | 3k views

The Archive page of the link mentioned as a reference by Arjun Sir (Original page is deleted now)

2 Answers

+39 votes
Best answer

Here we are comparing the execution time of only a single instruction. Pipelining in no way improves the execution time of a single instruction (the time from its start to end). It increases the overall performance by splitting the execution to multiple pipeline stages so that the following instructions can use the finished stages of the previous instructions. But in doing so pipelining causes some problems also as given in the below link, which might slow some instructions. So, (B) is the answer.

answered by Veteran (414k points)
edited by
Thanks !!!
What is the case for $T_1 = T_2$? (as it is implied by $T_1 \le T_2$)
when buffer delays are negligible in pipeline $T_1 = T_2$
@Arjun Sir, the link is not accesible. Error 404 : Not Found. Please check.
Thanks dude


Try this (Its saved page of that link)

thanks @smsubham
@thor T1=T2 when buffer delay is negligible as well as each stage delay are equal
@Arjun sir, in "Pipelining in no way increases the execution time of a single instruction" wouldn't "improves" instead of "increases" be more appropriate? Because pipelining does increase the execution time of a single instruction sometimes.
Thanks .You're correct .

 Sir If T1>t2 is one of the options along with T1>=T2 then which option to choose?

–4 votes
Everywhere answer given is (B) I cant understand why ... can anyone explain?

I am getting (A)
answered by Active (4k points)

- each stage takes "T" unit of time both in pipelined and non-pipelined setup.

- Total Pipeline Stages = K = Total number of stages in non-pipelined

- Number of Instructions = N = 1 in this case


TotalTime T1 = [K + (N-1)] * T = KT


TotalTime T2 = KNT = KT

Moreover there are intermediate buffers in between stages of pipelined processors which might consume some time. Therefore  T1 >= T2
@sameer2009 What is the K denote in Non-pipeline ?
Actually, K is number of stages via which an instruction will go through. Here K is independent whether processor is pipelined or non-pipelined.

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
49,811 questions
54,533 answers
75,574 users