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Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that

1. T1 ≤ T2
2. T1 ≥ T2
3. T1 < T2
4. T1 and T2 plus the time taken for one instruction fetch cycle

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Here we are comparing the execution time of only a single instruction. Pipelining in no way increases the execution time of a single instruction (the time from its start to end). It increases the overall performance by splitting the execution to multiple pipeline stages so that the following instructions can use the finished stages of the previous instructions. But in doing so pipelining causes some problems also as given in the below link, which might slow some instructions. So, (B) is the answer.

http://www.cs.wvu.edu/~jdm/classes/cs455/notes/tech/instrpipe.html

answered by Veteran (332k points)
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Thanks !!!
What is the case for $T_1 = T_2$? (as it is implied by $T_1 \le T_2$)
when buffer delays are negligible in pipeline $T_1 = T_2$
@Arjun Sir, the link is not accesible. Error 404 : Not Found. Please check.
Thanks dude

@rishi

Try this http://archive.is/XPYL (Its saved page of that link)

thanks @smsubham
Everywhere answer given is (B) I cant understand why ... can anyone explain?

I am getting (A)
answered by Loyal (3.8k points)
Suppose

- each stage takes "T" unit of time both in pipelined and non-pipelined setup.

- Total Pipeline Stages = K = Total number of stages in non-pipelined

- Number of Instructions = N = 1 in this case

Pipelined:

TotalTime T1 = [K + (N-1)] * T = KT

Non-Pipelined:

TotalTime T2 = KNT = KT

Moreover there are intermediate buffers in between stages of pipelined processors which might consume some time. Therefore  T1 >= T2
@sameer2009 What is the K denote in Non-pipeline ?
Actually, K is number of stages via which an instruction will go through. Here K is independent whether processor is pipelined or non-pipelined.