The Gateway to Computer Science Excellence
First time here? Checkout the FAQ!
+25 votes

The following arrangement of master-slave flip flops


has the initial state of P, Q as 0, 1 (respectively). After a clock cycle the output state P, Q is (respectively),

  1. 1, 0
  2. 1, 1
  3. 0, 0
  4. 0, 1
asked in Digital Logic by Veteran (59.8k points)
edited ago by | 3.1k views
after how many clock cycles?
How will I come to know that given diagram is for synchronous . According to me , Here output of 1st FF is given to 2nd FF .
I am not able to understand kindly help .
In synchronous counter, all the flip-flop responds to the same clock instance while in asynchronous counter the output of one FF drives the clock of another FF. And in the above, question clock is same for both the FF that's why the given dig. is for synchronous.
Thanks for replying !!

In asynchronous counter the output of 1 FF is given to other FF and I thnkt because of that it's Asynchronous .

Pleaee Correct me if I am wrong.

Yes, you are right that in asynchronous counter the output of 1FF is given to other FF but the output is given as the  Clock of other FF while in the synchronous we have same clock.

Please Correct me if I am wrong.


@ankitrokdeonsns you were right in some website and books it is written in question  "after three clock cycles"



After three clock cycle output states P,Q is 1,0 (no change in answer)

5 Answers

+39 votes
Best answer
Here clocks are applied to both flip flops simultaneously

When 11 is applied to jk flip flop it toggles the value of P so op at  P will be 1

Input to D flip flop will be 0( initial value of P)  so op at Q will be 0

So ans is a
answered by Boss (32.1k points)
edited by
JK-11 and previous state of P is 0, so next state of P will be 1. right?
but he is given to assume as master slave did it mean i need negation of the clock to the D-flip flop??

plz explain i am confused

@Arjun Sir,
IF the question were to calculate the output after 3 clock cycles  . Would the answer be 1,1...?
IS my approach correct ?

PC how do you get p=1 in cyle 2 when j=1,k=1 ,toggle happens it means previously p=1 after toggle p=0 na

u may get 01,10,01,10 ............
Yeah , u r correct . I did a mistake .

thx :)
It is given as a master slave FF then why the clock is not inverted for second FF?
Same Doubt!
The first FF is a master slave FF while 2nd one is a D FF, so the clock inversion happens within the first FF.
+17 votes

now when clock is aplied J= 1 and K=1 then (it do complement of P) i.,e output at p = 1 and at same time FF D has input 0 so it change Output Q as ) only [ on D-FF input = output]

SO output will be p= 1 and Q= 0 

[ keep in mind both FF work at same time dont wait for 1st complete then second will start].

answered by Veteran (61.4k points)

@sittian  hopw you got it now.

You are not getting this ia synchronous ckt I.e. clock is not present on any FF . Both FF work at together here .. Check clock input properly..

Input to D comes from JK FF not
+4 votes
first find the next state for jk-ff and d-ff  which is p(n+1)=not(p) and q(n+1)=d=p
given in question p=0 and q=1 so next state for p=1 and q=0
so a is ans
answered by (319 points)
+1 vote

-> As there is Master Slave configuration, 1st flipflop will respond to the positive edges and the 2nd flipflop to the negative edges.

-> As the given Flipflops are synchronous,(clock is simultaneously given to both FFs) $Q$ responds according to immediate values of $P$.

-> Thus, after 3 cycles, as shown in the diagram, $P = 1$ and $Q=0$ 

answered by (193 points)
0 votes

$Option A$

answered by Boss (10.9k points)

Related questions

Quick search syntax
tags tag:apple
author user:martin
title title:apple
content content:apple
exclude -tag:apple
force match +apple
views views:100
score score:10
answers answers:2
is accepted isaccepted:true
is closed isclosed:true
50,115 questions
53,224 answers
70,474 users