A processor (a core) is not a different entity.For example this above 5 stage pipeline datapath is built inside a typical processor which enables the system to run overlapping instruction. The control unit synchronizes all stage operations. On a particular common clock pulse the control unit activates control signals and depending on which each stage do it's functionality. Make sure that here, the processor is not fetching more than one instrutions simultaneously.(superscalar processor is irrelevent in our case).
out of order instruction is ok! Please tell little bit about stage out of order ?
I1 - I2 - I3 say these three are currently in the pipeline. I1 entered first,I2 second and I3 last.
You mean I2 can complete its execution before I1 does. right ?